
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case. This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
205 lines
7.4 KiB
C++
205 lines
7.4 KiB
C++
//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1InstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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using namespace llvm;
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Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI) {}
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/// Return the noop instruction to use for a noop.
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MCInst Thumb1InstrInfo::getNop() const {
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return MCInstBuilder(ARM::tMOVr)
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.addReg(ARM::R8)
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.addReg(ARM::R8)
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.addImm(ARMCC::AL)
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.addReg(0);
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}
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unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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return 0;
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}
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void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg,
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MCRegister SrcReg, bool KillSrc,
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bool RenamableDest, bool RenamableSrc) const {
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// Need to check the arch.
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MachineFunction &MF = *MBB.getParent();
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const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
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assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
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"Thumb1 can only copy GPR registers");
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if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) ||
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!ARM::tGPRRegClass.contains(DestReg))
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.add(predOps(ARMCC::AL));
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else {
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const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
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LiveRegUnits UsedRegs(*RegInfo);
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UsedRegs.addLiveOuts(MBB);
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auto InstUpToI = MBB.end();
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while (InstUpToI != I)
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// The pre-decrement is on purpose here.
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// We want to have the liveness right before I.
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UsedRegs.stepBackward(*--InstUpToI);
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if (UsedRegs.available(ARM::CPSR)) {
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BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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->addRegisterDead(ARM::CPSR, RegInfo);
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return;
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}
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// Use high register to move source to destination
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// if movs is not an option.
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BitVector Allocatable = RegInfo->getAllocatableSet(
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MF, RegInfo->getRegClass(ARM::hGPRRegClassID));
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Register TmpReg = ARM::NoRegister;
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// Prefer R12 as it is known to not be preserved anyway
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if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) {
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TmpReg = ARM::R12;
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} else {
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for (Register Reg : Allocatable.set_bits()) {
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if (UsedRegs.available(Reg)) {
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TmpReg = Reg;
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break;
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}
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}
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}
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if (TmpReg) {
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BuildMI(MBB, I, DL, get(ARM::tMOVr), TmpReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.add(predOps(ARMCC::AL));
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(TmpReg, getKillRegState(true))
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.add(predOps(ARMCC::AL));
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return;
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}
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// 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
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BuildMI(MBB, I, DL, get(ARM::tPUSH))
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.add(predOps(ARMCC::AL))
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.addReg(SrcReg, getKillRegState(KillSrc));
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BuildMI(MBB, I, DL, get(ARM::tPOP))
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.add(predOps(ARMCC::AL))
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.addReg(DestReg, getDefRegState(true));
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}
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}
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void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const {
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assert((RC == &ARM::tGPRRegClass ||
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(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
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"Unknown regclass!");
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if (RC == &ARM::tGPRRegClass ||
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(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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BuildMI(MBB, I, DL, get(ARM::tSTRspi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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}
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}
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void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const {
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assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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(DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
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"Unknown regclass!");
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if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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(DestReg.isPhysical() && isARMLowRegister(DestReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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}
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}
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void Thumb1InstrInfo::expandLoadStackGuard(
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MachineBasicBlock::iterator MI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
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const auto *GV = cast<GlobalValue>((*MI->memoperands_begin())->getValue());
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assert(MF.getFunction().getParent()->getStackProtectorGuard() != "tls" &&
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"TLS stack protector not supported for Thumb1 targets");
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unsigned Instr;
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if (!GV->isDSOLocal())
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Instr = ARM::tLDRLIT_ga_pcrel;
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else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
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Instr = ARM::t2MOVi32imm;
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else if (ST.genExecuteOnly())
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Instr = ARM::tMOVi32imm;
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else
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Instr = ARM::tLDRLIT_ga_abs;
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expandLoadStackGuardBase(MI, Instr, ARM::tLDRi);
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}
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bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
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// In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
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// but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
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// even if they have glue.
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// FIXME. Actually implement the cross-copy where it is possible (post v6)
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// because these copies entail more spilling.
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unsigned Opcode = N->getMachineOpcode();
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if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
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return true;
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return false;
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}
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