e13e95bc44
Do optimization to turn x >> (shift & 31/63) into a single srlv instead of andi + srlv, since the mips variable shift instruction already implicitly masks the shift, like x86, wasm and AMDGPU. Copy the X86DAGToDAGISel::isUnneededShiftMask() function to MIPS for checking whether need combine two instructions to one.
34 lines
1.3 KiB
TableGen
34 lines
1.3 KiB
TableGen
//===- MipsInstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various pseudo instructions used by the compiler,
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// as well as Pat patterns used during instruction selection.
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//
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//===----------------------------------------------------------------------===//
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def shiftMask_32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
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return isUnneededShiftMask(N, 5);
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}]>;
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def shiftMask_64 : PatFrag<(ops node:$src0), (and node:$src0, imm), [{
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return isUnneededShiftMask(N, 6);
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}]>;
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foreach width = [32, 64] in {
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defvar shiftMask = !cast<SDPatternOperator>("shiftMask_"#width);
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def mshl_#width : PatFrags<(ops node:$src0, node:$src1),
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[(shl node:$src0, node:$src1), (shl node:$src0, (shiftMask node:$src1))]>;
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def msrl_#width : PatFrags<(ops node:$src0, node:$src1),
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[(srl node:$src0, node:$src1), (srl node:$src0, (shiftMask node:$src1))]>;
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def msra_#width : PatFrags<(ops node:$src0, node:$src1),
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[(sra node:$src0, node:$src1), (sra node:$src0, (shiftMask node:$src1))]>;
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}
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