ee7ca0ddda
There are a number of backends (specifically AArch64, AMDGPU, Mips, and RISCV) which contain a “TODO: make CombinerHelper methods const” comment. This PR does just that and makes all of the CombinerHelper methods const, removes the TODO comments and makes the associated instances const. This change makes some sense because the CombinerHelper class simply modifies the state of _other_ objects to which it holds pointers or references. Note that AMDGPU contains an identical comment for an instance of AMDGPUCombinerHelper (a subclass of CombinerHelper). I deliberately haven’t modified the methods of that class in order to limit the scope of the change. I’m happy to do so either now or as a follow-up.
148 lines
5.1 KiB
C++
148 lines
5.1 KiB
C++
//=== lib/CodeGen/GlobalISel/MipsPreLegalizerCombiner.cpp --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsLegalizerInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/InitializePasses.h"
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#define DEBUG_TYPE "mips-prelegalizer-combiner"
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using namespace llvm;
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namespace {
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struct MipsPreLegalizerCombinerInfo : public CombinerInfo {
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public:
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MipsPreLegalizerCombinerInfo()
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, /*EnableOpt*/ false,
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/*EnableOptSize*/ false, /*EnableMinSize*/ false) {}
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};
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class MipsPreLegalizerCombinerImpl : public Combiner {
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protected:
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const MipsSubtarget &STI;
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const CombinerHelper Helper;
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public:
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MipsPreLegalizerCombinerImpl(MachineFunction &MF, CombinerInfo &CInfo,
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const TargetPassConfig *TPC, GISelKnownBits &KB,
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GISelCSEInfo *CSEInfo, const MipsSubtarget &STI,
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MachineDominatorTree *MDT,
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const LegalizerInfo *LI)
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: Combiner(MF, CInfo, TPC, &KB, CSEInfo), STI(STI),
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Helper(Observer, B, /*IsPreLegalize*/ true, &KB, MDT, LI) {}
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static const char *getName() { return "MipsPreLegalizerCombiner"; }
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void setupGeneratedPerFunctionState(MachineFunction &MF) override {
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// TODO: TableGen-erate this class' impl.
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}
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bool tryCombineAll(MachineInstr &MI) const override {
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switch (MI.getOpcode()) {
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default:
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return false;
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case TargetOpcode::G_MEMCPY_INLINE:
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return Helper.tryEmitMemcpyInline(MI);
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_SEXTLOAD:
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case TargetOpcode::G_ZEXTLOAD: {
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// Don't attempt to combine non power of 2 loads or unaligned loads when
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// subtarget doesn't support them.
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auto MMO = *MI.memoperands_begin();
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const MipsSubtarget &STI = MI.getMF()->getSubtarget<MipsSubtarget>();
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if (!MMO->getSize().hasValue() ||
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!isPowerOf2_64(MMO->getSize().getValue()))
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return false;
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bool isUnaligned = MMO->getAlign() < MMO->getSize().getValue();
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if (!STI.systemSupportsUnalignedAccess() && isUnaligned)
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return false;
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return Helper.tryCombineExtendingLoads(MI);
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}
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}
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return false;
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}
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};
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// Pass boilerplate
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// ================
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class MipsPreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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MipsPreLegalizerCombiner();
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StringRef getPassName() const override { return "MipsPreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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};
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} // end anonymous namespace
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void MipsPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MipsPreLegalizerCombiner::MipsPreLegalizerCombiner() : MachineFunctionPass(ID) {
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initializeMipsPreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool MipsPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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const MipsSubtarget &ST = MF.getSubtarget<MipsSubtarget>();
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const MipsLegalizerInfo *LI =
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static_cast<const MipsLegalizerInfo *>(ST.getLegalizerInfo());
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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MipsPreLegalizerCombinerInfo PCInfo;
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MipsPreLegalizerCombinerImpl Impl(MF, PCInfo, TPC, *KB, /*CSEInfo*/ nullptr,
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ST, /*MDT*/ nullptr, LI);
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return Impl.combineMachineInstrs();
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}
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char MipsPreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(MipsPreLegalizerCombiner, DEBUG_TYPE,
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"Combine Mips machine instrs before legalization", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_END(MipsPreLegalizerCombiner, DEBUG_TYPE,
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"Combine Mips machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createMipsPreLegalizeCombiner() {
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return new MipsPreLegalizerCombiner();
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}
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} // end namespace llvm
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