814b34f31e
This commit changes the branch emission logic so that instead of throwing the "branch target out of range" error, we emit a relocation instead.
107 lines
4.3 KiB
C++
107 lines
4.3 KiB
C++
//===-- RISCVAsmBackend.h - RISC-V Assembler Backend ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCAssembler;
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class MCObjectTargetWriter;
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class raw_ostream;
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class RISCVAsmBackend : public MCAsmBackend {
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const MCSubtargetInfo &STI;
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uint8_t OSABI;
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bool Is64Bit;
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bool ForceRelocs = false;
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const MCTargetOptions &TargetOptions;
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public:
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RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
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const MCTargetOptions &Options)
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: MCAsmBackend(llvm::endianness::little, RISCV::fixup_riscv_relax),
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STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
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RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
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}
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~RISCVAsmBackend() override = default;
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void setForceRelocs() { ForceRelocs = true; }
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// Return Size with extra Nop Bytes for alignment directive in code section.
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bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
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unsigned &Size) override;
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// Insert target specific fixup type for alignment directive in code section.
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bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
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MCAlignFragment &AF) override;
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bool evaluateTargetFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCFragment *DF, const MCValue &Target,
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const MCSubtargetInfo *STI, uint64_t &Value,
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bool &WasForced) override;
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bool handleAddSubRelocations(const MCAssembler &Asm, const MCFragment &F,
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const MCFixup &Fixup, const MCValue &Target,
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uint64_t &FixedValue) const override;
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override;
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override;
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, const uint64_t Value,
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const MCSubtargetInfo *STI) override;
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bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
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const MCFixup &Fixup, bool Resolved,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const bool WasForced) const override;
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unsigned getNumFixupKinds() const override {
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return RISCV::NumTargetFixupKinds;
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}
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std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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bool mayNeedRelaxation(const MCInst &Inst,
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const MCSubtargetInfo &STI) const override;
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unsigned getRelaxedOpcode(unsigned Op) const;
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override;
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bool relaxDwarfLineAddr(const MCAssembler &Asm, MCDwarfLineAddrFragment &DF,
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bool &WasRelaxed) const override;
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bool relaxDwarfCFA(const MCAssembler &Asm, MCDwarfCallFrameFragment &DF,
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bool &WasRelaxed) const override;
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std::pair<bool, bool> relaxLEB128(const MCAssembler &Asm, MCLEBFragment &LF,
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int64_t &Value) const override;
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override;
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const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
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};
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}
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#endif
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