8687f7cd66
Previously getIntImmInstCost only calculated the cost of materialising the argument of a store if it was the address. This means ConstantHoisting's transformation wouldn't kick in for cases like storing two values that require multiple instructions to materialise but where one can be cheaply generated from the other (e.g. by an addition). Two key changes were needed to avoid regressions when enabling this: * Allowing constant materialisation cost to be calculated assuming zeroes are free (as might happen if you had a 2*XLEN constant and one half is zero). * Avoiding constant hoisting if we have a misaligned store that's going to be a legalised to a sequence of narrower stores. I'm seeing cases where hoisting the constant ends up with worse codegen in that case. Out of caution and so as not to unexpectedly degrade other existing hoisting logic, FreeZeroes is used only for the new cost calculations for the load instruction. It would likely make sense to revisit this later.
84 lines
3.2 KiB
C++
84 lines
3.2 KiB
C++
//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCRegister.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include <cstdint>
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namespace llvm {
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class APInt;
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namespace RISCVMatInt {
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enum OpndKind {
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RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
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Imm, // LUI
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RegReg, // SH1ADD/SH2ADD/SH3ADD
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RegX0, // ADD_UW
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};
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class Inst {
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unsigned Opc;
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int32_t Imm; // The largest value we need to store is 20 bits.
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public:
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Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
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assert(I == Imm && "truncated");
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}
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unsigned getOpcode() const { return Opc; }
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int64_t getImm() const { return Imm; }
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OpndKind getOpndKind() const;
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};
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using InstSeq = SmallVector<Inst, 8>;
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// Helper to generate an instruction sequence that will materialise the given
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// immediate value into a register. A sequence of instructions represented by a
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// simple struct is produced rather than directly emitting the instructions in
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// order to allow this helper to be used from both the MC layer and during
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// instruction selection.
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InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);
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// Helper to generate the generateInstSeq instruction sequence using MCInsts
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void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
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MCRegister DestReg, SmallVectorImpl<MCInst> &Insts);
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// Helper to generate an instruction sequence that can materialize the given
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// immediate value into a register using an additional temporary register. This
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// handles cases where the constant can be generated by (ADD (SLLI X, C), X) or
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// (ADD_UW (SLLI X, C) X). The sequence to generate X is returned. ShiftAmt is
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// provides the SLLI and AddOpc indicates ADD or ADD_UW.
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InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
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unsigned &ShiftAmt, unsigned &AddOpc);
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// Helper to estimate the number of instructions required to materialise the
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// given immediate value into a register. This estimate does not account for
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// `Val` possibly fitting into an immediate, and so may over-estimate.
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//
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// This will attempt to produce instructions to materialise `Val` as an
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// `Size`-bit immediate.
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//
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// If CompressionCost is true it will use a different cost calculation if RVC is
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// enabled. This should be used to compare two different sequences to determine
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// which is more compressible.
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//
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// If FreeZeroes is true, it will be assumed free to materialize any
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// XLen-sized chunks that are 0. This is appropriate to use in instances when
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// the zero register can be used, e.g. when estimating the cost of
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// materializing a value used by a particular operation.
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int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
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bool CompressionCost = false, bool FreeZeroes = false);
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} // namespace RISCVMatInt
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} // namespace llvm
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#endif
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