124 lines
4.0 KiB
TableGen
124 lines
4.0 KiB
TableGen
//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SCR1: https://github.com/syntacore/scr1
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// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
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// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
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// same scheduling characteristics.
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// SCR1 is single-issue in-order processor
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def SyntacoreSCR1Model : SchedMachineModel {
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let MicroOpBufferSize = 0;
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let IssueWidth = 1;
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let LoadLatency = 2;
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let MispredictPenalty = 3;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
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HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
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HasVInstructions];
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}
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let SchedModel = SyntacoreSCR1Model in {
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let BufferSize = 0 in {
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def SCR1_ALU : ProcResource<1>;
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def SCR1_LSU : ProcResource<1>;
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def SCR1_MUL : ProcResource<1>;
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def SCR1_DIV : ProcResource<1>;
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def SCR1_CFU : ProcResource<1>;
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}
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// Branching
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def : WriteRes<WriteJmp, [SCR1_CFU]>;
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def : WriteRes<WriteJal, [SCR1_CFU]>;
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def : WriteRes<WriteJalr, [SCR1_CFU]>;
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// Integer arithmetic and logic
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def : WriteRes<WriteIALU32, [SCR1_ALU]>;
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def : WriteRes<WriteIALU, [SCR1_ALU]>;
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def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
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def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
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def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
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def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
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// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
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def : WriteRes<WriteIMul, [SCR1_MUL]>;
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def : WriteRes<WriteIMul32, [SCR1_MUL]>;
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// Integer division/remainder: latency 33, inverse throughput 33
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let Latency = 33, ReleaseAtCycles = [33] in {
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def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
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def : WriteRes<WriteIDiv, [SCR1_DIV]>;
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def : WriteRes<WriteIRem32, [SCR1_DIV]>;
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def : WriteRes<WriteIRem, [SCR1_DIV]>;
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}
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// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
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// (SCR1_CFG_RV32IMC_MAX includes TCM)
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let Latency = 2, ReleaseAtCycles=[2] in {
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// Memory
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def : WriteRes<WriteSTB, [SCR1_LSU]>;
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def : WriteRes<WriteSTH, [SCR1_LSU]>;
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def : WriteRes<WriteSTW, [SCR1_LSU]>;
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def : WriteRes<WriteSTD, [SCR1_LSU]>;
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def : WriteRes<WriteLDB, [SCR1_LSU]>;
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def : WriteRes<WriteLDH, [SCR1_LSU]>;
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def : WriteRes<WriteLDW, [SCR1_LSU]>;
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def : WriteRes<WriteLDD, [SCR1_LSU]>;
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}
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// Others
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def : WriteRes<WriteCSR, []>;
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def : WriteRes<WriteNop, []>;
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def : InstRW<[WriteIALU], (instrs COPY)>;
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//===----------------------------------------------------------------------===//
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// Bypasses (none)
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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//===----------------------------------------------------------------------===//
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// Unsupported extensions
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defm : UnsupportedSchedA;
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defm : UnsupportedSchedD;
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defm : UnsupportedSchedF;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedZba;
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defm : UnsupportedSchedZbb;
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defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbs;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}
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