llvm-project/llvm/test/DebugInfo/X86/codegenprepare-rollback.ll
Stephen Tozer 094572701d
[RemoveDIs] Print IR with debug records by default (#91724)
This patch makes the final major change of the RemoveDIs project, changing the
default IR output from debug intrinsics to debug records. This is expected to
break a large number of tests: every single one that tests for uses or
declarations of debug intrinsics and does not explicitly disable writing
records. 

If this patch has broken your downstream tests (or upstream tests on a
configuration I wasn't able to run):
1. If you need to immediately unblock a build, pass
`--write-experimental-debuginfo=false` to LLVM's option processing for all
failing tests (remember to use `-mllvm` for clang/flang to forward arguments to
LLVM).
2. For most test failures, the changes are trivial and mechanical, enough that
they can be done by script; see the migration guide for a guide on how to do
this: https://llvm.org/docs/RemoveDIsDebugInfo.html#test-updates
3. If any tests fail for reasons other than FileCheck check lines that need
updating, such as assertion failures, that is most likely a real bug with this
patch and should be reported as such.

For more information, see the recent PSA:
https://discourse.llvm.org/t/psa-ir-output-changing-from-debug-intrinsics-to-debug-records/79578
2024-06-14 15:07:27 +01:00

33 lines
1.3 KiB
LLVM

; RUN: opt -S -debugify -codegenprepare %s -o - | FileCheck %s --check-prefix=DEBUGIFY
; RUN: opt -S -debugify -codegenprepare %s -o - --try-experimental-debuginfo-iterators | FileCheck %s --check-prefix=DEBUGIFY
;
; Copied from codegen-prepare-addrmode-sext.ll -- for the twoArgsNoPromotion
; function, CGP attempts a type promotion transaction on the sext to replace
; it with %add, but then rolls it back. This involves re-inserting the sext
; instruction between two dbg.value intrinsics, and un-RAUWing the users of
; the sext.
; This test checks that this works correctly in both dbg.value mode, but also
; RemoveDIs non-intrinsic debug-info mode.
target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx"
; DEBUGIFY-LABEL: @twoArgsNoPromotion
; DEBUGIFY-NEXT: %add = add
; DEBUGIFY-NEXT: #dbg_value(i32 %add,
; DEBUGIFY-NEXT: %sextadd = sext
; DEBUGIFY-NEXT: #dbg_value(i64 %sextadd,
; DEBUGIFY-NEXT: %arrayidx = getelementptr
; DEBUGIFY-NEXT: #dbg_value(ptr %arrayidx,
; DEBUGIFY-NEXT: %res = load i8,
; DEBUGIFY-NEXT: #dbg_value(i8 %res,
; DEBUGIFY-NEXT: ret i8 %res,
define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, ptr %base) {
%add = add nsw i32 %arg1, %arg2
%sextadd = sext i32 %add to i64
%arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd
%res = load i8, ptr %arrayidx
ret i8 %res
}