a42053a1fa
CodeGenSchedModels::hasReadOfWrite tries to predicate whether the WriteDef is contained in the list of ValidWrites of someone ProcReadAdvance, so that WriteID of WriteDef can be compressed and reusable. It tries to iterate all ProcReadAdvance entry, but not all ProcReadAdvance defs also inherit from SchedRead. Some ProcReadAdvances are defined by ReadAdvance.So it's not complete to enumerate all ProcReadAdvances if just iterate all SchedReads. Differential Revision: https://reviews.llvm.org/D132205
55 lines
1.9 KiB
TableGen
55 lines
1.9 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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// Make sure that ReadAdvance entries are correctly processed.
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// Not all ProcReadAdvance definitions implicitly inherit from SchedRead.
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// Some ProcReadAdvances are subclasses of ReadAdvance.
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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let OutOperandList = (outs), InOperandList = (ins) in {
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def Inst_A : Instruction;
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def Inst_B : Instruction;
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def Inst_C : Instruction;
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}
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let CompleteModel = 0 in {
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def SchedModel_A: SchedMachineModel;
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}
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def Read_D : SchedRead;
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// CHECK: extern const llvm::MCWriteLatencyEntry MyTargetWriteLatencyTable[] = {
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// CHECK-NEXT: { 0, 0}, // Invalid
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// CHECK-NEXT: { 1, 0}, // #1 Write_A_Write_C
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// CHECK-NEXT: { 1, 2} // #2 Write_B
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// CHECK-NEXT: }; // MyTargetWriteLatencyTable
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// CHECK: extern const llvm::MCReadAdvanceEntry MyTargetReadAdvanceTable[] = {
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// CHECK-NEXT: {0, 0, 0}, // Invalid
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// CHECK-NEXT: {0, 2, 1} // #1
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// CHECK-NEXT: }; // MyTargetReadAdvanceTable
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// CHECK: static const llvm::MCSchedClassDesc SchedModel_ASchedClasses[] = {
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// CHECK-NEXT: {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
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// CHECK-NEXT: {DBGFIELD("Inst_A") 1, false, false, false, 0, 0, 1, 1, 0, 0}, // #1
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// CHECK-NEXT: {DBGFIELD("Inst_B") 1, false, false, false, 0, 0, 2, 1, 0, 0}, // #2
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// CHECK-NEXT: {DBGFIELD("Inst_C") 1, false, false, false, 0, 0, 1, 1, 1, 1}, // #3
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// CHECK-NEXT: }; // SchedModel_ASchedClasses
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let SchedModel = SchedModel_A in {
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def Write_A : SchedWriteRes<[]>;
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def Write_B : SchedWriteRes<[]>;
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def Write_C : SchedWriteRes<[]>;
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def : InstRW<[Write_A], (instrs Inst_A)>;
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def : InstRW<[Write_B], (instrs Inst_B)>;
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def : InstRW<[Write_C, Read_D], (instrs Inst_C)>;
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def : ReadAdvance<Read_D, 1, [Write_B]>;
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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