3097c60928
Currently it's very difficult to improve the cost model for tail-folded loops because as soon as you add a VPInstruction::computeCost function that adds the costs of instructions such as VPInstruction::ActiveLaneMask and VPInstruction::ExplicitVectorLength the assert in LoopVectorizationPlanner::computeBestVF fails for some tests. This is because the VF chosen by the legacy cost model doesn't match the vplan cost model. See PR #90191. This assert is currently making it difficult to improve the cost model. Hopefully we will be in a position to remove the assert soon, however in order to do that we have to fix up a whole bunch of tests that rely upon the legacy cost model output. I've tried my best to update these tests to use vplan output instead. There is still work needed for the VF=1 case because the vplan cost model is not printed out in this case. I've not attempted to fix those in this patch.
88 lines
3.1 KiB
LLVM
88 lines
3.1 KiB
LLVM
; RUN: opt -passes=loop-vectorize < %s -S -o - | FileCheck %s --check-prefix=CHECK
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; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -disable-output < %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
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; REQUIRES: asserts
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-none-none-eabi"
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; CHECK-LABEL: test
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; CHECK-COST: LV: Found an estimated cost of 0 for VF 1 For instruction: %and515 = shl i32 %l41, 3
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; CHECK-COST: LV: Found an estimated cost of 1 for VF 1 For instruction: %l45 = and i32 %and515, 131072
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; CHECK-COST: Cost of 2 for VF 4: WIDEN ir<%and515> = shl ir<%l41>, ir<3>
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; CHECK-COST: Cost of 2 for VF 4: WIDEN ir<%l45> = and ir<%and515>, ir<131072>
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; CHECK-NOT: vector.body
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define void @test(ptr %src, i32 %N) #0 {
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entry:
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br label %for.body386
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for.body386: ; preds = %entry, %l77
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%add387 = phi i32 [ %inc532, %l77 ], [ 0, %entry ]
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%arrayidx388 = getelementptr inbounds [101 x i32], ptr %src, i32 0, i32 %add387
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%l41 = load i32, ptr %arrayidx388, align 4
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%l42 = and i32 %l41, 65535
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%l43 = icmp eq i32 %l42, 0
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br i1 %l43, label %l77, label %l44
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l44: ; preds = %for.body386
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%and515 = shl i32 %l41, 3
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%l45 = and i32 %and515, 131072
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%and506 = shl i32 %l41, 5
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%l46 = and i32 %and506, 262144
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%and497 = shl i32 %l41, 7
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%l47 = and i32 %and497, 524288
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%and488 = shl i32 %l41, 9
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%l48 = and i32 %and488, 1048576
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%and479 = shl i32 %l41, 11
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%l49 = and i32 %and479, 2097152
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%and470 = shl i32 %l41, 13
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%l50 = and i32 %and470, 4194304
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%and461 = shl i32 %l41, 15
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%l51 = and i32 %and461, 8388608
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%and452 = shl i32 %l41, 17
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%l52 = and i32 %and452, 16777216
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%and443 = shl i32 %l41, 19
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%l53 = and i32 %and443, 33554432
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%and434 = shl i32 %l41, 21
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%l54 = and i32 %and434, 67108864
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%and425 = shl i32 %l41, 23
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%l55 = and i32 %and425, 134217728
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%and416 = shl i32 %l41, 25
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%l56 = and i32 %and416, 268435456
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%and407 = shl i32 %l41, 27
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%l57 = and i32 %and407, 536870912
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%and398 = shl i32 %l41, 29
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%l58 = and i32 %and398, 1073741824
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%l59 = shl i32 %l41, 31
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%l60 = or i32 %l59, %l41
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%l61 = or i32 %l58, %l60
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%l62 = or i32 %l57, %l61
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%l63 = or i32 %l56, %l62
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%l64 = or i32 %l55, %l63
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%l65 = or i32 %l54, %l64
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%l66 = or i32 %l53, %l65
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%l67 = or i32 %l52, %l66
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%l68 = or i32 %l51, %l67
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%l69 = or i32 %l50, %l68
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%l70 = or i32 %l49, %l69
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%l71 = or i32 %l48, %l70
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%l72 = or i32 %l47, %l71
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%l73 = or i32 %l46, %l72
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%l74 = or i32 %l45, %l73
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%and524 = shl i32 %l41, 1
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%l75 = and i32 %and524, 65536
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%l76 = or i32 %l75, %l74
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store i32 %l76, ptr %arrayidx388, align 4
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br label %l77
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l77: ; preds = %for.body386, %l44
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%inc532 = add nuw nsw i32 %add387, 1
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%exitcond649 = icmp eq i32 %inc532, %N
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br i1 %exitcond649, label %exit, label %for.body386
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exit:
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ret void
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}
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attributes #0 = { nounwind "min-legal-vector-width"="0" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+fp-armv8d16sp,+fp16,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp" "use-soft-float"="false" }
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