8ec406757c
This patch implements explicit unrolling by UF as VPlan transform. In follow up patches this will allow simplifying VPTransform state (no need to store unrolled parts) as well as recipe execution (no need to generate code for multiple parts in an each recipe). It also allows for more general optimziations (e.g. avoid generating code for recipes that are uniform-across parts). It also unifies the logic dealing with unrolled parts in a single place, rather than spreading it out across multiple places (e.g. VPlan post processing for header-phi recipes previously.) In the initial implementation, a number of recipes still take the unrolled part as additional, optional argument, if their execution depends on the unrolled part. The computation for start/step values for scalable inductions changed slightly. Previously the step would be computed as scalar and then splatted, now vscale gets splatted and multiplied by the step in a vector mul. This has been split off https://github.com/llvm/llvm-project/pull/94339 which also includes changes to simplify VPTransfomState and recipes' ::execute. The current version mostly leaves existing ::execute untouched and instead sets VPTransfomState::UF to 1. A follow-up patch will clean up all references to VPTransformState::UF. Another follow-up patch will simplify VPTransformState to only store a single vector value per VPValue. PR: https://github.com/llvm/llvm-project/pull/95842
71 lines
3.8 KiB
LLVM
71 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
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define float @for_load_interleave_only(ptr %src) {
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; CHECK-LABEL: define float @for_load_interleave_only(
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; CHECK-SAME: ptr [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 16000
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi float [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 16
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16
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; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP0]]
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; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[NEXT_GEP]], align 4
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; CHECK-NEXT: [[TMP3]] = load float, ptr [[NEXT_GEP2]], align 4
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; CHECK-NEXT: store float 0.000000e+00, ptr [[NEXT_GEP]], align 4
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; CHECK-NEXT: store float 0.000000e+00, ptr [[NEXT_GEP2]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
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; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1001, %[[MIDDLE_BLOCK]] ], [ 1, %[[ENTRY]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[SRC]], %[[ENTRY]] ]
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; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[FOR:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 16
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; CHECK-NEXT: [[L]] = load float, ptr [[PTR_IV]], align 4
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; CHECK-NEXT: store float 0.000000e+00, ptr [[PTR_IV]], align 4
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 1000
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[FOR_LCSSA:%.*]] = phi float [ [[FOR]], %[[LOOP]] ], [ [[TMP2]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret float [[FOR_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 1, %entry ], [ %iv.next, %loop ]
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%ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ]
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%for = phi float [ 0.000000e+00, %entry ], [ %l, %loop ]
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%iv.next = add i32 %iv, 1
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%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 16
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%l = load float, ptr %ptr.iv, align 4
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store float 0.000000e+00, ptr %ptr.iv, align 4
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%ec = icmp eq i32 %iv, 1000
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br i1 %ec, label %exit, label %loop
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exit:
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ret float %for
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
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;.
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