907c7eb311
This reverts commit e592c2dcf5b7d2da6c2564f5d9990aa34079bad4. We can finally reland the PR since the issue that caused the PR to be reverted has been resolved in https://github.com/llvm/llvm-project/pull/104051.
113 lines
5.1 KiB
LLVM
113 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
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target triple = "amdgcn-amd-amdhsa"
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%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy.8, ptr, ptr }
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%struct.ConfigurationEnvironmentTy.8 = type { i8, i8, i8, i32, i32, i32, i32, i32, i32 }
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@IsSPMDMode = internal addrspace(3) global i32 undef
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@__omp_offloading_10302_b20a40e_main_l4_kernel_environment = addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy.8 { i8 1, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) null to ptr), ptr addrspacecast (ptr addrspace(1) null to ptr) }
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;.
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; AMDGPU: @IsSPMDMode = internal addrspace(3) global i32 undef
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; AMDGPU: @__omp_offloading_10302_b20a40e_main_l4_kernel_environment = addrspace(1) constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy.8 { i8 0, i8 0, i8 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 }, ptr addrspacecast (ptr addrspace(1) null to ptr), ptr addrspacecast (ptr addrspace(1) null to ptr) }
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;.
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define i32 @fputs() {
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; AMDGPU-LABEL: define {{[^@]+}}@fputs
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; AMDGPU-SAME: () #[[ATTR0:[0-9]+]] {
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; AMDGPU-NEXT: fence acquire
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; AMDGPU-NEXT: ret i32 0
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;
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fence acquire
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ret i32 0
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}
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define internal i32 @__kmpc_target_init(ptr %0, ptr %dyn) {
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; AMDGPU-LABEL: define {{[^@]+}}@__kmpc_target_init
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; AMDGPU-SAME: (ptr [[TMP0:%.*]], ptr [[DYN:%.*]]) #[[ATTR1:[0-9]+]] {
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; AMDGPU-NEXT: [[TMP2:%.*]] = addrspacecast ptr getelementptr (i8, ptr addrspacecast (ptr addrspace(1) @__omp_offloading_10302_b20a40e_main_l4_kernel_environment to ptr), i64 2) to ptr addrspace(1)
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; AMDGPU-NEXT: [[TMP3:%.*]] = load i8, ptr addrspace(1) [[TMP2]], align 2
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; AMDGPU-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 2
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; AMDGPU-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
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; AMDGPU-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #[[ATTR3:[0-9]+]]
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; AMDGPU-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
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; AMDGPU-NEXT: [[OR_COND:%.*]] = select i1 [[TMP5]], i1 [[TMP7]], i1 false
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; AMDGPU-NEXT: br i1 [[OR_COND]], label [[TMP8:%.*]], label [[TMP9:%.*]]
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; AMDGPU: 8:
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; AMDGPU-NEXT: store i8 0, ptr addrspace(3) null, align 2147483648
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; AMDGPU-NEXT: br label [[TMP9]]
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; AMDGPU: 9:
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; AMDGPU-NEXT: br label [[TMP11:%.*]]
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; AMDGPU: 10:
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; AMDGPU-NEXT: unreachable
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; AMDGPU: 11:
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; AMDGPU-NEXT: ret i32 0
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;
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%2 = getelementptr %struct.ConfigurationEnvironmentTy.8, ptr %0, i64 0, i32 2
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%3 = load i8, ptr %2, align 2
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%4 = and i8 %3, 2
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%5 = icmp ne i8 %4, 0
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%6 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%7 = icmp eq i32 %6, 0
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%or.cond = select i1 %5, i1 %7, i1 false
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br i1 %or.cond, label %8, label %9
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8: ; preds = %1
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store i32 1, ptr addrspace(3) @IsSPMDMode, align 4
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store i8 0, ptr addrspace(3) null, align 2147483648
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br label %9
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9: ; preds = %8, %1
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%10 = load i32, ptr addrspace(3) @IsSPMDMode, align 4
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%11 = icmp eq i32 %10, 0
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br i1 %11, label %12, label %13
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12: ; preds = %9
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unreachable
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13: ; preds = %9
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ret i32 0
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare void @__kmpc_target_deinit()
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define amdgpu_kernel void @__omp_offloading_10302_b20a40e_main_l4(ptr %dyn) {
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; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_10302_b20a40e_main_l4
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; AMDGPU-SAME: (ptr [[DYN:%.*]]) {
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; AMDGPU-NEXT: [[TMP1:%.*]] = tail call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @__omp_offloading_10302_b20a40e_main_l4_kernel_environment to ptr), ptr [[DYN]]) #[[ATTR4:[0-9]+]]
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; AMDGPU-NEXT: br label [[TMP2:%.*]]
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; AMDGPU: 2:
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; AMDGPU-NEXT: [[TMP3:%.*]] = call i32 @fputs() #[[ATTR0]]
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; AMDGPU-NEXT: tail call void @__kmpc_target_deinit()
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; AMDGPU-NEXT: ret void
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;
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%1 = tail call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @__omp_offloading_10302_b20a40e_main_l4_kernel_environment to ptr), ptr %dyn)
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br label %2
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2: ; preds = %0
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%3 = call i32 @fputs()
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tail call void @__kmpc_target_deinit()
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ret void
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}
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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!llvm.module.flags = !{!0}
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!0 = !{i32 7, !"openmp", i32 51}
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;.
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; AMDGPU: attributes #[[ATTR0]] = { nounwind }
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; AMDGPU: attributes #[[ATTR1]] = { norecurse nosync nounwind }
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; AMDGPU: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; AMDGPU: attributes #[[ATTR3]] = { nosync }
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; AMDGPU: attributes #[[ATTR4]] = { nosync nounwind }
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;.
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; AMDGPU: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 51}
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;.
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