c3677e4522
This will help in later patches where the checks for operands being instructions is removed, and might help not remove unnecessary poison lanes.
39 lines
1.9 KiB
LLVM
39 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- | FileCheck %s
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target datalayout = "e-p:64:64-i64:64-f80:128-n8:16:32:64-S128"
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; This would insert before a phi instruction which is invalid IR.
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define <4 x double> @PR60649() {
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; CHECK-LABEL: @PR60649(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: unreachable:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[T0:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ zeroinitializer, [[UNREACHABLE:%.*]] ]
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; CHECK-NEXT: [[T1:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[UNREACHABLE]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP2:%.*]] = fdiv <4 x double> [[TMP1]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef>
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; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x double> [[TMP0]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef>
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; CHECK-NEXT: [[T5:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; CHECK-NEXT: ret <4 x double> [[T5]]
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;
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entry:
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br label %end
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unreachable:
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br label %end
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end:
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%t0 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ]
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%t1 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ]
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%t2 = shufflevector <4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
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%t3 = fdiv <4 x double> %t0, %t2
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%t4 = fmul <4 x double> %t0, %t2
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%t5 = shufflevector <4 x double> %t3, <4 x double> %t4, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x double> %t5
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}
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