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llvm-project/llvm/test/CodeGen/AMDGPU
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David Stuttard 46db606834 AMDGPU: Avoid folding 2 constant operands into an SALU operation 
Summary:
Catch the (admittedly unusual) case where SIFoldOperands attempts to fold 2
constant operands into the same SALU operation, with neither operand able to be
encoded as an inline constant.

Change-Id: Ibc48d662c9ffd8bbacd154976b0b1c257ace0927

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70896
2019-12-04 10:25:34 +00:00
..
GlobalISel
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
32-bit-local-address-space.ll
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accvgpr-copy.mir
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add3.ll
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add_i1.ll
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add_i64.ll
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add_i128.ll
…
add_shl.ll
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add-debug.ll
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add.i16.ll
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add.ll
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add.v2i16.ll
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addrspacecast-captured.ll
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addrspacecast-constantexpr.ll
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addrspacecast.ll
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adjust-writemask-invalid-copy.ll
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agpr-register-count.ll
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
alignbit-pat.ll
…
alloca.ll
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always-uniform.ll
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amdgcn-ieee.ll
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amdgcn.bitcast.ll
…
amdgcn.private-memory.ll
AMDGPU: Change boolean content type to 0 or 1
2019-11-15 13:43:47 +05:30
amdgpu-alias-analysis.ll
…
amdgpu-codegenprepare-fdiv.ll
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amdgpu-codegenprepare-i16-to-i32.ll
…
amdgpu-codegenprepare-idiv.ll
[IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator
2019-10-14 15:35:01 +00:00
amdgpu-codegenprepare-mul24.ll
…
amdgpu-function-calls-option.ll
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amdgpu-inline.ll
[AMDGPU] Tune inlining parameters for AMDGPU target (part 2)
2019-11-19 16:33:16 +03:00
amdgpu-shader-calling-convention.ll
…
amdgpu-unroll-threshold.ll
[AMDGPU] Add attribute for target loop unroll threshold default
2019-11-21 09:47:28 +00:00
amdgpu.private-memory.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
amdgpu.work-item-intrinsics.deprecated.ll
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amdhsa-trap-num-sgprs.ll
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amdpal_scratch_mergedshader.ll
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amdpal-cs.ll
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amdpal-es.ll
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amdpal-gs.ll
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amdpal-hs.ll
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amdpal-ls.ll
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amdpal-msgpack-cs.ll
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amdpal-msgpack-es.ll
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amdpal-msgpack-gs.ll
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amdpal-msgpack-hs.ll
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amdpal-msgpack-ls.ll
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amdpal-msgpack-ps.ll
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amdpal-msgpack-psenable.ll
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amdpal-msgpack-vs.ll
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amdpal-ps.ll
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amdpal-psenable.ll
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amdpal-vs.ll
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amdpal.ll
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and_or.ll
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and-gcn.ll
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and.ll
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andorbitset.ll
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andorn2.ll
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andorxorinvimm.ll
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annotate-kernel-features-hsa-call.ll
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annotate-kernel-features-hsa.ll
AMDGPU: Add intrinsics for address space identification
2019-09-05 02:20:39 +00:00
annotate-kernel-features.ll
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anonymous-gv.ll
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any_extend_vector_inreg.ll
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anyext.ll
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are-loads-from-same-base-ptr.ll
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array-ptr-calc-i32.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
array-ptr-calc-i64.ll
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ashr.v2i16.ll
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at-least-one-def-value-assert.mir
LiveIntervals: Remove assertion
2019-09-12 23:46:51 +00:00
atomic_cmp_swap_local.ll
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atomic_load_add.ll
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atomic_load_local.ll
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atomic_load_sub.ll
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atomic_optimizations_buffer.ll
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atomic_optimizations_global_pointer.ll
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atomic_optimizations_local_pointer.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
atomic_optimizations_pixelshader.ll
…
atomic_optimizations_raw_buffer.ll
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atomic_optimizations_struct_buffer.ll
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atomic_store_local.ll
…
atomicrmw-nand.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
attr-amdgpu-flat-work-group-size-v3.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
attr-amdgpu-flat-work-group-size.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
attr-amdgpu-num-sgpr.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-waves-per-eu.ll
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attr-unparseable.ll
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barrier-elimination.ll
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basic-branch.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
basic-call-return.ll
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basic-loop.ll
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bfe_uint.ll
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bfe-combine.ll
…
bfe-patterns.ll
…
bfi_int.ll
…
bfm.ll
…
big_alu.ll
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bitcast-constant-to-vector.ll
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bitcast-v4f16-v4i16.ll
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bitcast-vector-extract.ll
…
bitreverse-inline-immediates.ll
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bitreverse.ll
[AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition
2019-09-30 15:31:17 +00:00
br_cc.f16.ll
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branch-condition-and.ll
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branch-relax-bundle.ll
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branch-relax-spill.ll
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branch-relaxation-debug-info.ll
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branch-relaxation-inst-size-gfx10.ll
…
branch-relaxation.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
branch-uniformity.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
break-smem-soft-clauses.mir
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break-vmem-soft-clauses.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
bswap.ll
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buffer-intrinsics-mmo-offsets.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
buffer-schedule.ll
…
bug-vopc-commute.ll
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build_vector.ll
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build-vector-insert-elt-infloop.ll
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build-vector-packed-partial-undef.ll
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byval-frame-setup.ll
AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses
2019-09-05 23:54:35 +00:00
call_fs.ll
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call-argument-types.ll
AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses
2019-09-05 23:54:35 +00:00
call-constant.ll
AMDGPU: Don't error on calls to null or undef
2019-10-20 07:46:04 +00:00
call-constexpr.ll
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call-encoding.ll
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call-graph-register-usage.ll
[AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage
2019-11-06 15:47:32 -08:00
call-preserved-registers.ll
…
call-return-types.ll
…
call-skip.ll
…
call-to-kernel-undefined.ll
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call-to-kernel.ll
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call-waitcnt.ll
…
call-waw-waitcnt.mir
AMDGPU: Avoid overwriting saved PC
2019-10-28 10:02:22 -07:00
callee-frame-setup.ll
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callee-special-input-sgprs.ll
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callee-special-input-vgprs.ll
AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses
2019-09-05 23:54:35 +00:00
calling-conventions.ll
…
captured-frame-index.ll
…
cayman-loop-bug.ll
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cc-sgpr-limit.ll
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cc-sgpr-over-limit.ll
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cf_end.ll
…
cf-loop-on-constant.ll
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cf-stack-bug.ll
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cgp-addressing-modes-flat.ll
…
cgp-addressing-modes.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
cgp-bitfield-extract.ll
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chain-hi-to-lo.ll
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clamp-modifier.ll
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clamp-omod-special-case.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
clamp.ll
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cluster-flat-loads-postra.mir
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cluster-flat-loads.mir
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cndmask-no-def-vcc.ll
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coalescer_distribute.ll
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coalescer_remat.ll
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coalescer-extend-pruned-subrange.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-identical-values-undef.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-subranges-another-copymi-not-live.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-subranges-another-prune-error.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-subregjoin-fullcopy.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-with-subregs-bad-identical.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescing-with-subregs-in-loop-bug.mir
…
code-object-v3.ll
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codegen-prepare-addrmode-sext.ll
…
collapse-endcf2.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
collapse-endcf-broken.mir
…
collapse-endcf.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
collapse-endcf.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
combine_vloads.ll
…
combine-and-sext-bool.ll
…
combine-cond-add-sub.ll
AMDGPU: Change boolean content type to 0 or 1
2019-11-15 13:43:47 +05:30
combine-ftrunc.ll
…
comdat.ll
…
commute_modifiers.ll
…
commute-compares.ll
…
commute-shifts.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
[amdgpu] Fix known bits compuation on MUL_I24/MUL_U24.
2019-11-01 17:06:17 -04:00
concat_vectors.ll
…
constant-address-space-32bit.ll
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constant-fold-imm-immreg.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
constant-fold-mi-operands.ll
…
control-flow-fastregalloc.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
control-flow-optnone.ll
…
convergent-inlineasm.ll
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copy-illegal-type.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
copy-to-reg.ll
…
couldnt-join-subrange-3.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
cross-block-use-is-not-abi-copy.ll
…
cse-phi-incoming-val.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
csr-gfx10.ll
…
ctlz_zero_undef.ll
…
ctlz.ll
…
ctpop16.ll
…
ctpop64.ll
…
ctpop.ll
…
cttz_zero_undef.ll
…
cube.ll
…
cvt_f32_ubyte.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dag-divergence.ll
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dagcomb-shuffle-vecextend-non2.ll
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dagcombine-reassociate-bug.ll
…
dagcombine-select.ll
…
dagcombine-setcc-select.ll
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dagcombiner-bug-illegal-vec4-int-to-fp.ll
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dce-disjoint-intervals.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
dead_copy.mir
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dead-lane.mir
…
dead-mi-use-same-intr.mir
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debug-value2.ll
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debug-value-scheduler-crash.mir
…
debug-value.ll
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debug.ll
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default-fp-mode.ll
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detect-dead-lanes.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
directive-amdgcn-target.ll
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disable_form_clauses.ll
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disconnected-predset-break-bug.ll
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div_i128.ll
…
diverge-extra-formal-args.ll
…
diverge-interp-mov-lower.ll
…
diverge-switch-default.ll
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divergence-at-use.ll
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divergent-branch-uniform-condition.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
divrem24-assume.ll
[IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator
2019-10-14 15:35:01 +00:00
dpp_combine.ll
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
dpp_combine.mir
[AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required)
2019-10-25 21:30:37 +03:00
drop-mem-operand-move-smrd.ll
…
ds_read2_offset_order.ll
…
ds_read2_superreg.ll
…
ds_read2.ll
…
ds_read2st64.ll
…
ds_write2.ll
…
ds_write2st64.ll
…
ds-combine-large-stride.ll
…
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
ds-sub-offset.ll
…
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
…
early-if-convert.ll
…
early-inline-alias.ll
…
early-inline.ll
…
elf-header-flags-mach.ll
…
elf-header-flags-sram-ecc.ll
…
elf-header-flags-xnack.ll
…
elf-header-osabi.ll
…
elf-notes.ll
…
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
else.ll
…
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
…
enqueue-kernel.ll
…
exceed-max-sgprs.ll
…
extend-bit-ops-i16.ll
…
extload-align.ll
…
extload-private.ll
…
extload.ll
…
extract_subvector_vec4_vec3.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
extract_vector_dynelt.ll
AMDGPU: Change boolean content type to 0 or 1
2019-11-15 13:43:47 +05:30
extract_vector_elt-f16.ll
…
extract_vector_elt-f64.ll
…
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
…
extract_vector_elt-i64.ll
…
extract-lowbits.ll
…
extract-subvector-equal-length.ll
AMDGPU: Remove optnone from a test
2019-10-19 01:34:59 +00:00
extract-vector-elt-build-vector-combine.ll
…
extractelt-to-trunc.ll
…
fabs.f16.ll
…
fabs.f64.ll
…
fabs.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fadd64.ll
…
fadd-fma-fmul-combine.ll
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fadd.f16.ll
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fadd.ll
…
fcanonicalize-elimination.ll
…
fcanonicalize.f16.ll
…
fcanonicalize.ll
…
fceil64.ll
…
fceil.ll
…
fcmp64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
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fcmp.ll
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fconst64.ll
…
fcopysign.f16.ll
…
fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv32-to-rcp-folding.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fdiv.f16.ll
…
fdiv.f64.ll
…
fdiv.ll
[DAGCombiner] Improve division estimation of floating points.
2019-09-12 07:51:24 +00:00
fdot2.ll
…
fence-barrier.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
fetch-limits.r600.ll
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fetch-limits.r700+.ll
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fexp.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
ffloor.f64.ll
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ffloor.ll
…
fix-sgpr-copies.mir
AMDGPU: Fix infinite searches in SIFixSGPRCopies
2019-10-15 19:59:45 +00:00
fix-vgpr-copies.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
fix-wwm-vgpr-copy.ll
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flat_atomics_i64.ll
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flat_atomics.ll
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flat-address-space.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
flat-error-unsupported-gpu-hsa.ll
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flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
flat-offset-bug.ll
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flat-scratch-reg.ll
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floor.ll
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fma-combine.ll
…
fma.f64.ll
[AMDGPU] Improve fma.f64 test. NFC.
2019-09-25 18:50:34 +00:00
fma.ll
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fmac.sdwa.ll
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fmad.ll
…
fmax3.f64.ll
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fmax3.ll
…
fmax_legacy.f16.ll
…
fmax_legacy.f64.ll
…
fmax_legacy.ll
…
fmax.ll
…
fmaxnum.f64.ll
…
fmaxnum.ll
…
fmaxnum.r600.ll
…
fmed3.ll
…
fmin3.ll
…
fmin_fmax_legacy.amdgcn.ll
…
fmin_legacy.f16.ll
…
fmin_legacy.f64.ll
…
fmin_legacy.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fmin.ll
…
fminnum.f64.ll
…
fminnum.ll
…
fminnum.r600.ll
…
fmul64.ll
…
fmul-2-combine-multi-use.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fmul.f16.ll
…
fmul.ll
…
fmuladd.f16.ll
[AMDGPU] Fix test checks
2019-10-07 10:57:41 +00:00
fmuladd.f32.ll
…
fmuladd.f64.ll
…
fmuladd.v2f16.ll
…
fnearbyint.ll
…
fneg-combines.ll
AMDGPU/GlobalISel: Select G_FABS/G_FNEG
2019-09-10 17:19:46 +00:00
fneg-combines.si.ll
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fneg-fabs.f16.ll
…
fneg-fabs.f64.ll
…
fneg-fabs.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fneg.f16.ll
…
fneg.f64.ll
…
fneg.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fold_acc_copy_into_valu.mir
[AMDGPU] Fix illegal agpr use by VALU
2019-10-02 23:23:46 +00:00
fold-cndmask.mir
…
fold-fi-mubuf.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
fold-fi-operand-shrink.mir
…
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir
[AMDGPU] Skip additional folding on the same operand.
2019-10-24 11:30:22 -04:00
fold-imm-f16-f32.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
fold-implicit-operand.mir
…
fold-multiple.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
fold-operands-order.mir
…
fold-operands-remove-m0-redef.mir
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands
2019-10-21 19:53:46 +00:00
fold-over-exec.mir
[AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition
2019-09-30 15:31:17 +00:00
fold-readlane.mir
…
fold-reload-into-m0.mir
AMDGPU: Disallow spill folding with m0 copies
2019-10-30 14:56:33 -07:00
fold-sgpr-copy.mir
[AMDGPU] Enable SGPR copy folding
2019-10-25 15:08:30 -07:00
fold-sgpr-multi-imm.mir
AMDGPU: Avoid folding 2 constant operands into an SALU operation
2019-12-04 10:25:34 +00:00
fold-vgpr-copy.mir
[AMDGPU] Allow folding of sgpr to vgpr copy
2019-10-23 18:42:48 -07:00
force-alwaysinline-lds-global-address-codegen.ll
…
force-alwaysinline-lds-global-address.ll
…
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp_to_sint.f64.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
…
fp_to_uint.ll
…
fp-atomic-to-s_denormmode.mir
…
fp-classify.ll
…
fpext-free.ll
…
fpext.f16.ll
…
fpext.ll
…
fptosi.f16.ll
…
fptoui.f16.ll
…
fptrunc.f16.ll
…
fptrunc.ll
[SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.
2019-10-30 15:18:21 +00:00
fract.f64.ll
…
fract.ll
…
frame-index-elimination.ll
AMDGPU: Inline constant when materalizing FI with add on gfx9
2019-09-12 23:46:46 +00:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
…
frem.ll
…
fsqrt.f64.ll
…
fsqrt.ll
…
fsub64.ll
…
fsub.f16.ll
…
fsub.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll
…
function-call-relocs.ll
…
function-returns.ll
…
gds-atomic.ll
…
gep-address-space.ll
…
gfx10-vop-literal.ll
…
gfx902-without-xnack.ll
…
global_atomics_i64.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
global_atomics.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
global_smrd_cfg.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
global_smrd.ll
…
global-atomics-fp.ll
AMDGPU: Select global atomicrmw fadd
2019-11-06 16:06:38 -08:00
global-constant.ll
Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"
2019-09-02 14:40:57 +00:00
global-directive.ll
…
global-extload-i16.ll
…
global-load-store-atomics.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
global-saddr.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
global-smrd-unknown.ll
…
global-variable-relocs.ll
…
gv-const-addrspace.ll
…
gv-offset-folding.ll
…
gws-hazards.mir
…
half.ll
…
hazard-buffer-store-v-interp.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
hazard-hidden-bundle.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
hazard-in-bundle.mir
…
hazard-inlineasm.mir
…
hazard-kill.mir
…
hazard.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
hoist-cond.ll
…
hsa-default-device.ll
…
hsa-fp-mode.ll
…
hsa-func-align.ll
…
hsa-func.ll
…
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll
…
hsa-metadata-deduce-ro-arg.ll
…
hsa-metadata-enqueue-kernel-v3.ll
…
hsa-metadata-enqueue-kernel.ll
…
hsa-metadata-from-llvm-ir-full-v3.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-from-llvm-ir-full.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-hidden-args-v3.ll
…
hsa-metadata-hidden-args.ll
…
hsa-metadata-hostcall-absent-v3.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-absent.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-present-v3.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-hostcall-present.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
hsa-metadata-images-v3.ll
…
hsa-metadata-images.ll
…
hsa-metadata-invalid-ocl-version-1-v3.ll
…
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-2-v3.ll
…
hsa-metadata-invalid-ocl-version-2.ll
…
hsa-metadata-invalid-ocl-version-3-v3.ll
…
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props-v3.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
hsa-metadata-kernel-code-props.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
hsa-metadata-wavefrontsize.ll
…
hsa-note-no-func.ll
…
hsa.ll
…
huge-private-buffer.ll
…
i1_copy_phi_with_phi_incoming_value.mir
[AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.
2019-10-26 14:37:45 +05:30
i1-copies-rpo.mir
…
i1-copy-from-loop.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
i1-copy-phi.ll
…
i8-to-double-to-float.ll
…
icmp64.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
idiv-licm.ll
…
idot2.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
idot4s.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
idot4u.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
idot8s.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
idot8u.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
illegal-sgpr-to-vgpr-copy.ll
[AMDGPU] Fix illegal agpr use by VALU
2019-10-02 23:23:46 +00:00
image_ls_mipmap_zero.ll
…
image-attributes.ll
…
image-resource-id.ll
…
image-schedule.ll
…
img-nouse-adjust.ll
…
imm16.ll
…
imm.ll
…
immv216.ll
…
implicit-def-muse.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
indirect-addressing-si-gfx9.ll
…
indirect-addressing-si-noopt.ll
[SDAG] fold extract_vector_elt with undef index
2019-10-25 19:27:26 -04:00
indirect-addressing-si-pregfx9.ll
…
indirect-addressing-si.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
indirect-addressing-term.ll
AMDGPU: Stop adding m0 implicit def to SGPR spills
2019-10-21 19:42:29 +00:00
indirect-private-64.ll
…
infer-addrpace-pipeline.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll
…
inline-asm.ll
AMDGPU: Make VReg_1 only include 1 artificial register
2019-10-28 20:51:51 -07:00
inline-attr.ll
…
inline-calls.ll
…
inline-constraints.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inline-maxbb.ll
…
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
…
InlineAsmCrash.ll
…
input-mods.ll
…
insert_subreg.ll
…
insert_vector_dynelt.ll
…
insert_vector_elt.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
insert_vector_elt.v2i16.ll
…
insert_vector_elt.v2i16.subtest-nosaddr.ll
…
insert_vector_elt.v2i16.subtest-saddr.ll
…
insert-skip-from-vcc.mir
…
insert-skips-flat-vmem.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
insert-skips-gws.mir
…
insert-skips-ignored-insts.mir
…
insert-skips-kill-uncond.mir
…
insert-subvector-unused-scratch.ll
…
insert-waitcnts-callee.mir
…
insert-waitcnts-exp.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
inserted-wait-states.mir
[AMDGPU] Fix-up cases where writelane has 2 SGPR operands
2019-10-16 14:37:39 +00:00
internalize.ll
…
invalid-addrspacecast.ll
…
invalid-alloca.ll
…
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
ipra-regmask.ll
…
ipra.ll
…
jump-address.ll
…
kcache-fold.ll
…
kernarg-stack-alignment.ll
…
kernel-args.ll
…
kernel-argument-dag-lowering.ll
…
known-never-nan.ll
…
known-never-snan.ll
…
knownbits-recursion.ll
…
large-alloca-compute.ll
…
large-alloca-graphics.ll
…
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
lcssa-optnone.ll
…
lds_atomic_f32.ll
…
lds-alignment.ll
…
lds-bounds.ll
…
lds-branch-vmem-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
lds-global-non-entry-func.ll
…
lds-initializer.ll
…
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
…
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll
…
lds-size.ll
…
lds-zero-initializer.ll
…
legalize-fp-load-invariant.ll
…
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
lit.local.cfg
…
literals.ll
…
liveness.mir
…
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.dec.ll
…
llvm.amdgcn.atomic.fadd.ll
…
llvm.amdgcn.atomic.inc.ll
…
llvm.amdgcn.buffer.atomic.ll
…
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.format.d16.ll
…
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll
…
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.buffer.store.format.d16.ll
…
llvm.amdgcn.buffer.store.format.ll
…
llvm.amdgcn.buffer.store.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
…
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
…
llvm.amdgcn.cubeid.ll
…
llvm.amdgcn.cubema.ll
…
llvm.amdgcn.cubesc.ll
…
llvm.amdgcn.cubetc.ll
…
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
…
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
…
llvm.amdgcn.div.scale.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.gws.barrier.ll
…
llvm.amdgcn.ds.gws.init.ll
[IR] Fix mayReadFromMemory() for writeonly calls
2019-10-21 06:52:08 +00:00
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.p.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
…
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.ll
…
llvm.amdgcn.ds.ordered.swap.ll
…
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
…
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmad.ftz.f16.ll
…
llvm.amdgcn.fmad.ftz.ll
…
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
…
llvm.amdgcn.frexp.exp.f16.ll
…
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.ll
…
llvm.amdgcn.image.a16.dim.ll
…
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.d16.dim.ll
…
llvm.amdgcn.image.dim.ll
…
llvm.amdgcn.image.gather4.a16.dim.ll
…
llvm.amdgcn.image.gather4.d16.dim.ll
…
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.a16.d16.ll
…
llvm.amdgcn.image.load.a16.ll
…
llvm.amdgcn.image.nsa.ll
…
llvm.amdgcn.image.sample.a16.dim.ll
…
llvm.amdgcn.image.sample.d16.dim.ll
…
llvm.amdgcn.image.sample.dim.ll
…
llvm.amdgcn.image.sample.ltolz.ll
…
llvm.amdgcn.image.sample.o.dim.ll
…
llvm.amdgcn.image.store.a16.d16.ll
…
llvm.amdgcn.image.store.a16.ll
…
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
…
llvm.amdgcn.implicitarg.ptr.ll
…
llvm.amdgcn.init.exec.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.init.exec.wave32.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.f16.ll
AMDGPU: Use CopyToReg for interp intrinsic lowering
2019-10-21 19:53:49 +00:00
llvm.amdgcn.interp.ll
…
llvm.amdgcn.is.private.ll
AMDGPU: Add intrinsics for address space identification
2019-09-05 02:20:39 +00:00
llvm.amdgcn.is.shared.ll
AMDGPU: Add intrinsics for address space identification
2019-09-05 02:20:39 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.kill.ll
…
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
…
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.ll
AMDGPU: Fix lit test checks with dag option
2019-11-28 10:01:06 +00:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Fixed dpp test. NFC.
2019-11-13 16:38:54 -08:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.permlane.ll
…
llvm.amdgcn.ps.live.ll
…
llvm.amdgcn.qsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.ll
…
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll
…
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
…
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.tbuffer.load.ll
…
llvm.amdgcn.raw.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.tbuffer.store.ll
…
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
…
llvm.amdgcn.readfirstlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.readlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
2019-09-06 10:07:28 +00:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32
2019-11-15 15:01:15 +01:00
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
…
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
…
llvm.amdgcn.s.memtime.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
…
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.sendmsg.ll
…
llvm.amdgcn.set.inactive.ll
…
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
…
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.ll
…
llvm.amdgcn.struct.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.buffer.load.format.ll
…
llvm.amdgcn.struct.buffer.load.ll
…
llvm.amdgcn.struct.buffer.store.format.d16.ll
…
llvm.amdgcn.struct.buffer.store.format.ll
…
llvm.amdgcn.struct.buffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll
…
llvm.amdgcn.struct.tbuffer.load.ll
…
llvm.amdgcn.struct.tbuffer.store.d16.ll
…
llvm.amdgcn.struct.tbuffer.store.ll
…
llvm.amdgcn.tbuffer.load.d16.ll
…
llvm.amdgcn.tbuffer.load.dwordx3.ll
…
llvm.amdgcn.tbuffer.load.ll
…
llvm.amdgcn.tbuffer.store.d16.ll
…
llvm.amdgcn.tbuffer.store.dwordx3.ll
…
llvm.amdgcn.tbuffer.store.ll
…
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
…
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Support mov dpp with 64 bit operands
2019-10-15 16:41:15 +00:00
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wavefrontsize.ll
…
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.ceil.f16.ll
…
llvm.cos.f16.ll
…
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.exp2.f16.ll
…
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll
…
llvm.fmuladd.f16.ll
…
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll
…
llvm.log10.ll
…
llvm.log.f16.ll
…
llvm.log.ll
…
llvm.maxnum.f16.ll
…
llvm.memcpy.ll
…
llvm.minnum.f16.ll
…
llvm.pow.ll
…
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
…
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
…
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
…
llvm.round.ll
…
llvm.sin.f16.ll
…
llvm.sin.ll
…
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll
…
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
…
load-constant-i8.ll
…
load-constant-i16.ll
…
load-constant-i32.ll
…
load-constant-i64.ll
…
load-global-f32.ll
…
load-global-f64.ll
…
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll
…
load-global-i32.ll
…
load-global-i64.ll
…
load-hi16.ll
…
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
…
load-local-f64.ll
…
load-local-i1.ll
…
load-local-i8.ll
…
load-local-i16.ll
…
load-local-i32.ll
…
load-local-i64.ll
…
load-select-ptr.ll
…
load-weird-sizes.ll
…
local-64.ll
…
local-atomics64.ll
…
local-atomics-fp.ll
…
local-atomics.ll
…
local-memory.amdgcn.ll
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
2019-09-06 10:07:28 +00:00
local-memory.ll
…
local-memory.r600.ll
…
local-stack-slot-offset.ll
…
loop_break.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
loop_exit_with_xor.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
loop_header_nopred.mir
Remove assert from MachineLoop::getLoopPredecessor()
2019-09-20 15:26:10 +00:00
loop-address.ll
…
loop-idiom.ll
…
lower-kernargs.ll
…
lower-mem-intrinsics.ll
…
lower-range-metadata-intrinsic-call.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
lshl64-to-32.ll
…
lshr.v2i16.ll
(Re)generate various tests. NFC
2019-10-08 16:16:26 +00:00
macro-fusion-cluster-vcc-uses.mir
…
mad24-get-global-id.ll
…
mad_64_32.ll
…
mad_int24.ll
…
mad_uint24.ll
…
mad-combine.ll
…
mad-mix-hi.ll
…
mad-mix-lo.ll
…
mad-mix.ll
…
mad.u16.ll
…
madak-inline-constant.mir
…
madak.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
madmk.ll
…
mai-hazards.mir
…
mai-inline.ll
…
max3.ll
…
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
…
max.ll
[AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests.
2019-09-19 16:44:38 +00:00
mcp-overlap-after-propagation.mir
MCP: Fixed bug with dest overlapping copy source
2019-11-12 08:18:11 +00:00
med3-no-simplify.ll
…
mem-builtins.ll
…
memory_clause.ll
…
memory_clause.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
memory-legalizer-amdpal.ll
…
memory-legalizer-atomic-cmpxchg.ll
…
memory-legalizer-atomic-fence.ll
…
memory-legalizer-atomic-insert-end.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
memory-legalizer-atomic-rmw.ll
…
memory-legalizer-invalid-addrspace.mir
…
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-load.ll
…
memory-legalizer-local.mir
…
memory-legalizer-mesa3d.ll
…
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
memory-legalizer-region.mir
…
memory-legalizer-store-infinite-loop.ll
…
memory-legalizer-store.ll
…
merge-image-load.mir
[AMDGPU] Extend the SI Load/Store optimizer
2019-10-16 10:17:02 +00:00
merge-image-sample.mir
[AMDGPU] Extend the SI Load/Store optimizer
2019-10-16 10:17:02 +00:00
merge-load-store-physreg.mir
AMDGPU: Remove unnecessary IR from test
2019-10-14 18:30:29 +00:00
merge-load-store-vreg.mir
…
merge-load-store.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
merge-m0.mir
AMDGPU: Move m0 initializations earlier
2019-09-11 21:28:41 +00:00
merge-store-crash.ll
…
merge-store-usedef.ll
…
merge-stores.ll
…
merge-tbuffer.mir
[AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/stores
2019-11-20 22:59:30 +01:00
mesa3d.ll
…
mesa_regression.ll
…
mfma-loop.ll
[AMDGPU] Fixed mfma-loop test. NFC.
2019-11-13 16:03:54 -08:00
min3.ll
…
min.ll
…
mir-print-dead-csr-fi.mir
…
misched-killflags.mir
…
missing-store.ll
…
mixed_wave32_wave64.ll
…
mixed-wave32-wave64.ll
…
mode-register.mir
…
move-addr64-rsrc-dead-subreg-writes.ll
…
move-to-valu-atomicrmw.ll
…
move-to-valu-worklist.ll
…
movreld-bug.ll
…
movrels-bug.mir
…
mubuf-legalize-operands.ll
…
mubuf-legalize-operands.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
mubuf-offset-private.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll
…
mul24-pass-ordering.ll
…
mul_int24.ll
…
mul_uint24-amdgcn.ll
…
mul_uint24-r600.ll
…
mul.i16.ll
…
mul.ll
…
multi-divergent-exit-region.ll
…
multi-dword-vgpr-spill.ll
…
multilevel-break.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
nand.ll
…
nested-calls.ll
…
nested-loop-conditions.ll
…
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll
Use -mtriple to fix AMDGPU test sensitive to object file format
2019-09-05 00:34:01 +00:00
no-remat-indirect-mov.mir
…
no-shrink-extloads.ll
…
noop-shader-O0.ll
…
nop-data.ll
…
nop-fold.mir
AMDGPU: Don't fold S_NOPs with implicit operands
2019-10-30 14:40:56 -07:00
nor.ll
…
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
…
nsa-vmem-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
nullptr.ll
…
occupancy-levels.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
offset-split-flat.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
offset-split-global.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
omod-nsz-flag.mir
AMDGPU: Be explicit about denormal mode in MIR tests
2019-11-19 19:55:43 +05:30
omod.ll
…
opencl-image-metadata.ll
…
opencl-printf-no-hostcall.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
opencl-printf.ll
…
operand-folding.ll
[AMDGPU] Skip additional folding on the same operand.
2019-10-24 11:30:22 -04:00
operand-spacing.ll
…
opt-sgpr-to-vgpr-copy.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
optimize-exec-masking-pre-ra.mir
AMDGPU: Propagate undef flag during pre-RA exec mask optimizations
2019-10-08 12:46:32 +00:00
optimize-if-exec-masking.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
optimize-negated-cond-exec-masking-wave32.mir
…
optimize-negated-cond-exec-masking.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
optimize-negated-cond.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
or3.ll
…
or.ll
…
pack.v2f16.ll
…
pack.v2i16.ll
…
packed-op-sel.ll
…
packetizer.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll
…
partial-shift-shrink.ll
…
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir
…
pei-reg-scavenger-position.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
pei-scavenge-sgpr-carry-out.mir
AMDGPU: Reuse carry out register during FI elimination
2019-11-28 10:13:48 -08:00
pei-scavenge-sgpr-gfx9.mir
AMDGPU: Inline constant when materalizing FI with add on gfx9
2019-09-12 23:46:46 +00:00
pei-scavenge-sgpr.mir
AMDGPU: Don't use frame virtual registers
2019-08-29 01:13:47 +00:00
perfhint.ll
…
permute.ll
…
phi-elimination-assertion.mir
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
2019-09-17 09:08:58 +00:00
phi-elimination-end-cf.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
…
postra-norename.mir
…
power-sched-no-instr-sunit.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
print-mir-custom-pseudo.ll
…
private-access-no-objects.ll
…
private-element-size.ll
…
private-memory-atomics.ll
…
private-memory-r600.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-addrspacecast.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-globals.ll
…
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll
…
promote-alloca-no-opts.ll
…
promote-alloca-padding-size-estimate.ll
…
promote-alloca-stored-pointer-value.ll
…
promote-alloca-to-lds-icmp.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-phi.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-select.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll
…
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
[AMDGPU] Keep consistent check of legal addressing mode.
2019-11-20 15:08:17 -05:00
promote-constOffset-to-imm.ll
[AMDGPU] Keep consistent check of legal addressing mode.
2019-11-20 15:08:17 -05:00
promote-constOffset-to-imm.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
propagate-attributes-bitcast-function.ll
…
propagate-attributes-clone.ll
…
propagate-attributes-single-set.ll
…
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"
2019-09-02 14:40:57 +00:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
…
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
…
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
rcp_iflag.ll
…
rcp-pattern.ll
…
read_register.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
readcyclecounter.ll
…
readlane_exec0.mir
…
README
…
reassoc-scalar.ll
…
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll
…
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
…
reg-coalescer-sched-crash.ll
…
regbank-reassign.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
regcoal-subrange-join-seg.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
regcoal-subrange-join.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescing-remove-partial-redundancy-assert.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
register-count-comments.ll
…
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
rename-independent-subregs.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
reorder-stores.ll
…
reqd-work-group-size.ll
…
ret_jump.ll
…
ret.ll
…
returnaddress.ll
…
rewrite-out-arguments-address-space.ll
…
rewrite-out-arguments.ll
…
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll
[DAGCombiner] Improve division estimation of floating points.
2019-09-12 07:51:24 +00:00
rv7x0_count3.ll
…
s_addk_i32.ll
…
s_code_end.ll
…
s_movk_i32.ll
…
s_mulk_i32.ll
…
sad.ll
…
saddo.ll
[AMDGPU] Allow folding of sgpr to vgpr copy
2019-10-23 18:42:48 -07:00
salu-to-valu.ll
…
sampler-resource-id.ll
…
scalar_to_vector_v2x16.ll
…
scalar_to_vector.ll
…
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir
…
sched-assert-dead-def-subreg-use-other-subreg.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
sched-assert-onlydbg-value-empty-region.mir
…
sched-crash-dbg-value.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
LiveIntervals: Fix handleMoveUp with subreg def moving across a def
2019-10-18 23:24:25 +00:00
schedule-barrier.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit2.ll
…
schedule-regpressure-limit3.ll
…
schedule-regpressure-limit.ll
…
schedule-regpressure.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
scheduler-handle-move-bundle.mir
…
scheduler-subrange-crash.ll
…
scratch-buffer.ll
…
scratch-simple.ll
…
sdiv.ll
…
sdivrem24.ll
…
sdivrem64.ll
…
sdwa-gfx9.mir
…
sdwa-op64-test.ll
…
sdwa-ops.mir
…
sdwa-peephole-instr-gfx10.mir
…
sdwa-peephole-instr.mir
…
sdwa-peephole.ll
AMDGPU: Fix i16 arithmetic pattern redundancy
2019-10-08 17:36:38 +00:00
sdwa-preserve.mir
…
sdwa-scalar-ops.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
sdwa-vop2-64bit.mir
…
select64.ll
…
select-fabs-fneg-extract-legacy.ll
…
select-fabs-fneg-extract.ll
…
select-i1.ll
…
select-opt.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
select-undef.ll
…
select-vectors.ll
…
select.f16.ll
…
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
…
sendmsg-m0-hazard.mir
…
set-dx10.ll
…
setcc64.ll
…
setcc-equivalent.ll
…
setcc-fneg-constant.ll
…
setcc-limit-load-shrink.ll
…
setcc-opt.ll
…
setcc-sext.ll
…
setcc.ll
…
seto.ll
…
setuo.ll
…
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
…
sgpr-control-flow.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
sgpr-spill-wrong-stack-id.mir
…
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll
…
shift-i64-opts.ll
…
shift-i128.ll
…
shl_add_constant.ll
…
shl_add_ptr.ll
…
shl_add.ll
…
shl_or.ll
…
shl-add-to-add-shl.ll
…
shl.ll
…
shl.v2i16.ll
(Re)generate various tests. NFC
2019-10-08 16:16:26 +00:00
shrink-add-sub-constant.ll
…
shrink-carry.mir
…
shrink-vop3-carry-out.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
si-annotate-cf-noloop.ll
…
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
si-annotate-cfg-loop-assert.ll
…
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies.mir
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
si-i1-copies.mir
MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block
2019-10-08 12:46:20 +00:00
si-instr-info-correct-implicit-operands.ll
…
si-lower-control-flow-kill.ll
…
si-lower-control-flow-unreachable-block.ll
…
si-lower-control-flow.mir
…
si-lower-i1-copies.mir
…
si-lower-sgpr-spills.mir
…
si-scheduler.ll
…
si-sgpr-spill.ll
…
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
si-triv-disjoint-mem-access.ll
…
si-vector-hang.ll
…
sibling-call.ll
…
sign_extend.ll
…
simplify-libcalls.ll
Revert "Revert "As a follow-up to my initial mail to llvm-dev here's a first pass at the O1 described there.""
2019-11-26 20:28:52 -08:00
simplifydemandedbits-recursion.ll
…
sint_to_fp.f64.ll
…
sint_to_fp.i64.ll
…
sint_to_fp.ll
…
sitofp.f16.ll
…
skip-branch-taildup-ret.mir
…
skip-branch-trap.ll
…
skip-if-dead.ll
…
smed3.ll
…
smem-no-clause-coalesced.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
smem-war-hazard.mir
AMDGPU: Fix SMEM WAR hazard for gfx10 readlane
2019-10-18 18:20:30 +00:00
sminmax.ll
[AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests.
2019-09-19 16:44:38 +00:00
sminmax.v2i16.ll
[AMDGPU] Unnecessary -amdgpu-scalarize-global-loads=false flag removed from min/max lit tests.
2019-09-19 16:44:38 +00:00
smrd-fold-offset.mir
…
smrd-gfx10.ll
…
smrd-vccz-bug.ll
[AMDGPU] Simplify VCCZ bug handling
2019-10-30 17:09:07 +00:00
smrd.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
sopk-compares.ll
…
sp-too-many-input-sgprs.ll
…
spill-agpr.ll
…
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
…
spill-empty-live-interval.mir
…
spill-m0.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
spill-offset-calculation.ll
…
spill-scavenge-offset.ll
…
spill-vgpr-to-agpr.ll
…
spill-wide-sgpr.ll
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
2019-10-18 21:48:22 +00:00
split-arg-dbg-value.ll
[AMDGPU] Remove update_llc_test_checks for a test
2019-10-25 11:47:33 -04:00
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
…
splitkit.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
sra.ll
…
sram-ecc-default.ll
…
srem.ll
…
srl.ll
…
ssubo.ll
…
stack-pointer-offset-relative-frameindex.ll
AMDGPU: Don't fold copies to physregs
2019-10-09 22:51:42 +00:00
stack-realign-kernel.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
stack-realign.ll
…
stack-size-overflow.ll
…
stack-slot-color-sgpr-vgpr-spills.mir
AMDGPU: Stop adding m0 implicit def to SGPR spills
2019-10-21 19:42:29 +00:00
store_typed.ll
…
store-barrier.ll
…
store-global.ll
…
store-hi16.ll
AMDGPU: Split flat offsets that don't fit in DAG
2019-10-20 17:34:44 +00:00
store-local.ll
…
store-private.ll
…
store-v3i64.ll
…
store-vector-ptrs.ll
…
store-weird-sizes.ll
…
stress-calls.ll
…
structurize1.ll
…
structurize.ll
…
sub_i1.ll
…
sub.i16.ll
…
sub.ll
…
sub.v2i16.ll
…
subreg_interference.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
subreg-undef-def-with-other-subreg-defs.mir
MachineScheduler: Fix missing dependency with multiple subreg defs
2019-09-20 00:09:15 +00:00
subvector-test.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
swizzle-export.ll
…
syncscopes.ll
…
tail-call-cgp.ll
…
tail-duplication-convergent.ll
…
target-cpu.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
trap.ll
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
…
trunc-combine.ll
…
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
…
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
…
tti-unroll-prefs.ll
…
twoaddr-fma.mir
[AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16
2019-09-18 09:32:06 +00:00
twoaddr-mad.mir
[AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16
2019-09-18 09:32:06 +00:00
uaddo.ll
…
udiv.ll
…
udivrem24.ll
…
udivrem64.ll
…
udivrem.ll
…
uint_to_fp.f64.ll
…
uint_to_fp.i64.ll
…
uint_to_fp.ll
…
uitofp.f16.ll
…
umed3.ll
…
unaligned-load-store.ll
…
undefined-physreg-sgpr-spill.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
undefined-subreg-liverange.ll
…
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
…
uniform-crash.ll
…
uniform-loop-inside-nonuniform.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
uniform-work-group-attribute-missing.ll
…
uniform-work-group-nested-function-calls.ll
…
uniform-work-group-prevent-attribute-propagation.ll
…
uniform-work-group-propagate-attribute.ll
…
uniform-work-group-recursion-test.ll
…
uniform-work-group-test.ll
…
unify-metadata.ll
…
unigine-liveness-crash.ll
…
unknown-processor.ll
…
unpack-half.ll
…
unroll.ll
…
unsupported-calls.ll
AMDGPU: Don't error on calls to null or undef
2019-10-20 07:46:04 +00:00
unsupported-cc.ll
…
update-phi.ll
…
urem.ll
…
use-sgpr-multiple-times.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
usubo.ll
…
v1i64-kernel-arg.ll
…
v1024.ll
…
v_cndmask.ll
…
v_cvt_pk_u8_f32.ll
…
v_mac_f16.ll
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
2019-09-06 10:07:28 +00:00
v_mac.ll
…
v_madak_f16.ll
…
v_swap_b32.mir
…
valu-i1.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
vccz-corrupt-bug-workaround.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
vcmpx-exec-war-hazard.mir
…
vcmpx-permlane-hazard.mir
…
vector_shuffle.packed.ll
…
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca.ll
…
vector-extract-insert.ll
…
vector-legalizer-divergence.ll
…
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
verify-sop.mir
…
vertex-fetch-encoding.ll
…
vgpr-descriptor-waterfall-loop-idom-update.ll
AMDGPU: Fix the broken dominator tree when creating waterfall loop for resource descriptor
2019-10-25 13:08:04 -07:00
vgpr-spill-emergency-stack-slot-compute.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
vgpr-spill-emergency-stack-slot.ll
…
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
…
vmem-to-salu-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
vmem-vcc-hazard.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
vop-shrink-frame-index.mir
…
vop-shrink-non-ssa.mir
…
vop-shrink.ll
…
vselect64.ll
…
vselect.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
…
waitcnt-back-edge-loop.mir
…
waitcnt-debug.mir
…
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
waitcnt-loop-single-basic-block.mir
…
waitcnt-looptest.ll
…
waitcnt-no-redundant.mir
…
waitcnt-overflow.mir
AMDGPU: Handle waitcnt overflow
2019-11-23 09:34:23 -08:00
waitcnt-permute.mir
…
waitcnt-preexisting.mir
…
waitcnt-vscnt.ll
[AMDGPU] Mark s_barrier as having side effects but not accessing memory.
2019-09-06 10:07:28 +00:00
waitcnt.mir
…
wave32.ll
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
wave_dispatch_regs.ll
…
widen_extending_scalar_loads.ll
…
widen-smrd-loads.ll
…
widen-vselect-and-mask.ll
…
wqm.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
wqm.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
write_register.ll
…
write-register-vgpr-into-sgpr.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reserved.ll
…
xfail.r600.bitcast.ll
…
xnor.ll
…
xor3-i1-const.ll
…
xor3.ll
…
xor_add.ll
…
xor.ll
…
zero_extend.ll
…
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.