2024-10-09 19:18:36 +00:00
|
|
|
module spram
|
|
|
|
(
|
|
|
|
input wire clk,
|
|
|
|
input wire [3:0] we,
|
|
|
|
input wire [13:0] addr,
|
|
|
|
input wire [15:0] data_in,
|
|
|
|
output wire [15:0] data_out
|
|
|
|
);
|
|
|
|
|
2024-10-17 15:11:06 +00:00
|
|
|
`ifdef VERILATOR
|
|
|
|
reg [15:0] mem[16384];
|
2024-10-09 19:18:36 +00:00
|
|
|
|
2024-10-17 15:11:06 +00:00
|
|
|
reg [15:0] data_out_r;
|
2024-10-09 19:18:36 +00:00
|
|
|
|
2024-10-17 15:11:06 +00:00
|
|
|
always_ff @(posedge clk) begin
|
|
|
|
integer i;
|
2024-10-09 19:18:36 +00:00
|
|
|
for (i = 0; i < 4; i = i + 1) begin
|
2024-10-17 15:11:06 +00:00
|
|
|
if (we[i]) begin
|
|
|
|
mem[addr][(3+4*i)+:4] <= data_in[(3+4*i)+:4];
|
|
|
|
end
|
2024-10-09 19:18:36 +00:00
|
|
|
end
|
2024-10-17 15:11:06 +00:00
|
|
|
|
|
|
|
data_out_r <= mem[addr];
|
|
|
|
end
|
2024-10-09 19:18:36 +00:00
|
|
|
|
2024-10-17 15:11:06 +00:00
|
|
|
assign data_out = data_out_r;
|
|
|
|
`else
|
|
|
|
SP256K bb_spram_inst(.AD(addr), .DI(data_in), .MASKWE(we), .WE(|we), .CS('1), .CK(clk), .STDBY('0), .SLEEP('0), .PWROFF_N('1), .DO(data_out));
|
|
|
|
`endif
|
2024-10-09 19:18:36 +00:00
|
|
|
|
|
|
|
endmodule
|