41 lines
896 B
Systemverilog
41 lines
896 B
Systemverilog
|
module coords
|
||
|
|
#(
|
||
|
|
parameter WIDTH = 128,
|
||
|
|
parameter HEIGHT = 128,
|
||
|
|
parameter POS_COUNT = 4,
|
||
|
|
localparam WIDTH_BITS = $clog2(WIDTH),
|
||
|
|
localparam HEIGHT_BITS = $clog2(HEIGHT)
|
||
|
|
)(
|
||
|
|
input wire clk,
|
||
|
|
input wire rst,
|
||
|
|
output reg [WIDTH_BITS-1:0] x[POS_COUNT],
|
||
|
|
output reg [WIDTH_BITS-1:0] y[POS_COUNT],
|
||
|
|
output wire finished
|
||
|
|
);
|
||
|
|
|
||
|
|
reg [POS_COUNT-1:0] finished_r;
|
||
|
|
|
||
|
|
always_ff @(posedge clk) begin
|
||
|
|
integer i;
|
||
|
|
if (rst) begin
|
||
|
|
for (i = 0; i < POS_COUNT; i = i + 1) begin
|
||
|
|
x[i] <= WIDTH_BITS'(i);
|
||
|
|
y[i] <= 0;
|
||
|
|
end
|
||
|
|
finished_r <= '1;
|
||
|
|
end else begin
|
||
|
|
for (i = 0; i < POS_COUNT; i = i + 1) begin
|
||
|
|
x[i] <= WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH);
|
||
|
|
if (x[i] > WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH)) begin
|
||
|
|
y[i] <= y[i] + 1;
|
||
|
|
if (y[i] > HEIGHT_BITS'((32'(y[i]) + 1) % HEIGHT)) begin
|
||
|
|
finished_r[i] <= 0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign finished = finished_r == 0;
|
||
|
|
|
||
|
|
endmodule
|