22 lines
339 B
Systemverilog
22 lines
339 B
Systemverilog
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module multiplier
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(
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input wire clk,
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input wire signed [7:0] a,
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input wire signed [7:0] b,
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output reg signed [15:0] product
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);
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reg signed [7:0] a_reg;
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reg signed [7:0] b_reg;
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wire [15:0] product_out;
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always_ff @(posedge clk) begin
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a_reg <= a;
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b_reg <= b;
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product <= product_out;
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end
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assign product_out = a_reg * b_reg;
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endmodule
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