diff --git a/ice/constraints.sdc b/ice/constraints.sdc
index c480413..b02d443 100644
--- a/ice/constraints.sdc
+++ b/ice/constraints.sdc
@@ -1 +1 @@
-create_clock -period 20.8333333 [get_ports {clk}]
\ No newline at end of file
+create_clock -period 125 [get_ports {clk}]
\ No newline at end of file
diff --git a/ice/coords.sv b/ice/coords.sv
new file mode 100644
index 0000000..9dc49e9
--- /dev/null
+++ b/ice/coords.sv
@@ -0,0 +1,41 @@
+module coords
+#(
+	parameter WIDTH = 128,
+	parameter HEIGHT = 128,
+	parameter POS_COUNT = 4,
+	localparam WIDTH_BITS = $clog2(WIDTH),
+	localparam HEIGHT_BITS = $clog2(HEIGHT)
+)(
+	input wire clk,
+	input wire rst,
+	output reg [WIDTH_BITS-1:0] x[POS_COUNT],
+	output reg [WIDTH_BITS-1:0] y[POS_COUNT],
+	output wire finished
+);
+
+reg [POS_COUNT-1:0] finished_r;
+
+always_ff @(posedge clk) begin
+	integer i;
+	if (rst) begin
+		for (i = 0; i < POS_COUNT; i = i + 1) begin
+			x[i] <= WIDTH_BITS'(i);
+			y[i] <= 0;
+		end
+		finished_r <= '1;
+	end else begin
+		for (i = 0; i < POS_COUNT; i = i + 1) begin
+			x[i] <= WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH);
+			if (x[i] > WIDTH_BITS'((32'(x[i]) + POS_COUNT) % WIDTH)) begin
+				y[i] <= y[i] + 1;
+				if (y[i] > HEIGHT_BITS'((32'(y[i]) + 1) % HEIGHT)) begin
+					finished_r[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+assign finished = finished_r == 0;
+
+endmodule
\ No newline at end of file
diff --git a/ice/mandelbrot/.ng_run_manager.ini b/ice/mandelbrot/.ng_run_manager.ini
index 2d2a62a..593d2b6 100644
--- a/ice/mandelbrot/.ng_run_manager.ini
+++ b/ice/mandelbrot/.ng_run_manager.ini
@@ -1,6 +1,6 @@
 [Runmanager]
 Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x3\0\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x14\0\0\x1\xca\0\0\0\xb9)
-headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x15\0\xf0\x1f\0\0\0\t\0\0\0\f\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x10\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\x5\xf\0\0\0\x15\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x84\0\0\0\0\0\0\0\x15\0\0\0\xc3\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\x3\xe8\0\0\0\0\x64)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x15\0\xf0\x1f\0\0\0\t\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\f\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\0\x10\0\0\0\x64\0\0\x5\xf\0\0\0\x15\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x84\0\0\0\0\0\0\0\x15\0\0\0\xc3\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\x64\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x1\0\0\0\0\0\0\x3\xe8\0\0\0\0\x64)
 
 [impl_1%3CStrategy1%3E]
 isChecked=false
diff --git a/ice/mandelbrot/.recovery b/ice/mandelbrot/.recovery
index 233b638..112931f 100644
--- a/ice/mandelbrot/.recovery
+++ b/ice/mandelbrot/.recovery
@@ -2,12 +2,21 @@
 <RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
     <Options/>
     <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="top"/>
+        <Options def_top="top" top="top"/>
         <Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
-            <Options VerilogStandard="System Verilog"/>
+            <Options VerilogStandard="System Verilog" top_module="top"/>
         </Source>
         <Source name="../ram.sv" type="Verilog" type_short="Verilog">
-            <Options VerilogStandard="System Verilog" top_module="RAM"/>
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../coords.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="source/impl_1/renderer.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="source/impl_1/multiplier.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
         </Source>
         <Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC">
             <Options/>
diff --git a/ice/mandelbrot/mandelbrot.rdf b/ice/mandelbrot/mandelbrot.rdf
index d0ea781..7c87ea9 100644
--- a/ice/mandelbrot/mandelbrot.rdf
+++ b/ice/mandelbrot/mandelbrot.rdf
@@ -2,13 +2,22 @@
 <RadiantProject version="4.2" radiant="2024.1.0.34.2" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
     <Options/>
     <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
-        <Options/>
+        <Options def_top="renderer" top="top"/>
         <Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog" top_module="top"/>
         </Source>
         <Source name="../ram.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
+        <Source name="../coords.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="source/impl_1/renderer.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="source/impl_1/multiplier.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../constraints.pdc" type="Physical Constraints File" type_short="PDC">
             <Options/>
         </Source>
diff --git a/ice/mandelbrot/mandelbrot_tcl.html b/ice/mandelbrot/mandelbrot_tcl.html
index 7e8dc3f..4934044 100644
--- a/ice/mandelbrot/mandelbrot_tcl.html
+++ b/ice/mandelbrot/mandelbrot_tcl.html
@@ -178,12 +178,112 @@ prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/ra
 
 
 
+<A name="pn241003133906"></A><B><U><big>pn241003133906</big></U></B>
+#Start recording tcl command: 10/2/2024 11:19:00
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
+prj_run PAR -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Export -impl impl_1
+prj_run Synthesis -impl impl_1
+#Stop recording: 10/3/2024 13:39:06
+
+
+
+<A name="pn241004114221"></A><B><U><big>pn241004114221</big></U></B>
+#Start recording tcl command: 10/3/2024 13:54:22
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Export -impl impl_1
+prj_set_impl_opt -impl "impl_1" "top" "top"
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+#Stop recording: 10/4/2024 11:42:21
+
+
+
+<A name="pn241004151504"></A><B><U><big>pn241004151504</big></U></B>
+#Start recording tcl command: 10/4/2024 13:54:24
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_run Synthesis -impl impl_1
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/coords.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/renderer.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/multiplier.sv"
+#Stop recording: 10/4/2024 15:15:04
+
+
+
 </PRE></DIV>
 
 <DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
 <UL id="toc_list">
 <LI><A href=#pn240928081403>pn240928081403</A></LI>
 <LI><A href=#pn241002102238>pn241002102238</A></LI>
+<LI><A href=#pn241003133906>pn241003133906</A></LI>
+<LI><A href=#pn241004114221>pn241004114221</A></LI>
+<LI><A href=#pn241004151504>pn241004151504</A></LI>
 </UL>
 </DIV>
 
diff --git a/ice/mandelbrot/mandelbrot_tcr.dir/pn241003133906.tcr b/ice/mandelbrot/mandelbrot_tcr.dir/pn241003133906.tcr
new file mode 100644
index 0000000..e030376
--- /dev/null
+++ b/ice/mandelbrot/mandelbrot_tcr.dir/pn241003133906.tcr
@@ -0,0 +1,56 @@
+#Start recording tcl command: 10/2/2024 11:19:00
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/color_converter.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
+prj_run PAR -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Export -impl impl_1
+prj_run Synthesis -impl impl_1
+#Stop recording: 10/3/2024 13:39:06
diff --git a/ice/mandelbrot/mandelbrot_tcr.dir/pn241004114221.tcr b/ice/mandelbrot/mandelbrot_tcr.dir/pn241004114221.tcr
new file mode 100644
index 0000000..2c1fee3
--- /dev/null
+++ b/ice/mandelbrot/mandelbrot_tcr.dir/pn241004114221.tcr
@@ -0,0 +1,20 @@
+#Start recording tcl command: 10/3/2024 13:54:22
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
+prj_run Synthesis -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Map -impl impl_1
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_run Synthesis -impl impl_1
+prj_run Export -impl impl_1
+prj_set_impl_opt -impl "impl_1" "top" "top"
+prj_run PAR -impl impl_1
+prj_run Export -impl impl_1
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/xd.sv"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/framebuffer.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+#Stop recording: 10/4/2024 11:42:21
diff --git a/ice/mandelbrot/mandelbrot_tcr.dir/pn241004151504.tcr b/ice/mandelbrot/mandelbrot_tcr.dir/pn241004151504.tcr
new file mode 100644
index 0000000..404f9eb
--- /dev/null
+++ b/ice/mandelbrot/mandelbrot_tcr.dir/pn241004151504.tcr
@@ -0,0 +1,9 @@
+#Start recording tcl command: 10/4/2024 13:54:24
+#Project Location: C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot; Project name: mandelbrot
+prj_open "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/mandelbrot.rdf"
+prj_remove_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/fifo.sv"
+prj_run Synthesis -impl impl_1
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/coords.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/renderer.sv"
+prj_add_source "C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/source/impl_1/multiplier.sv"
+#Stop recording: 10/4/2024 15:15:04
diff --git a/ice/mandelbrot/promote.xml b/ice/mandelbrot/promote.xml
index 992e339..730cffd 100644
--- a/ice/mandelbrot/promote.xml
+++ b/ice/mandelbrot/promote.xml
@@ -1,3 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<userSetting name="C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/promote.xml" version="Diamond (64-bit) 2024.1.0.34.2" date="Wed Oct 02 12:34:15 2024" vendor="Lattice Semiconductor Corporation" >
+<userSetting name="C:/Users/fuzzc/Documents/Hardware/pico-ice/pico-ice-video/ice/mandelbrot/promote.xml" version="Diamond (64-bit) 2024.1.0.34.2" date="Sun Oct 06 00:16:13 2024" vendor="Lattice Semiconductor Corporation" >
 </userSetting>
diff --git a/ice/mandelbrot/source/impl_1/.gitignore b/ice/mandelbrot/source/impl_1/.gitignore
new file mode 100644
index 0000000..697cf4f
--- /dev/null
+++ b/ice/mandelbrot/source/impl_1/.gitignore
@@ -0,0 +1 @@
+obj_dir/
diff --git a/ice/mandelbrot/source/impl_1/makefile b/ice/mandelbrot/source/impl_1/makefile
new file mode 100644
index 0000000..63c42b6
--- /dev/null
+++ b/ice/mandelbrot/source/impl_1/makefile
@@ -0,0 +1,6 @@
+run: build
+	cd obj_dir && ./Vtop && gtkwave waveform.vcd
+
+build:
+	verilator --trace --cc top.sv --exe tb_top.cpp -I../../..
+	make -C obj_dir -f Vtop.mk Vtop
diff --git a/ice/mandelbrot/source/impl_1/multiplier.sv b/ice/mandelbrot/source/impl_1/multiplier.sv
new file mode 100644
index 0000000..4eaff0f
--- /dev/null
+++ b/ice/mandelbrot/source/impl_1/multiplier.sv
@@ -0,0 +1,22 @@
+module multiplier
+(
+	input wire clk,
+	input wire signed [7:0] a,
+	input wire signed [7:0] b,
+	output reg signed [15:0] product
+);
+
+reg signed [7:0] a_reg;
+reg signed [7:0] b_reg;
+
+wire [15:0] product_out;
+
+always_ff @(posedge clk) begin
+	a_reg <= a;
+	b_reg <= b;
+	product <= product_out;
+end
+
+assign product_out = a_reg * b_reg;
+
+endmodule
\ No newline at end of file
diff --git a/ice/mandelbrot/source/impl_1/renderer.sv b/ice/mandelbrot/source/impl_1/renderer.sv
new file mode 100644
index 0000000..1fb9d65
--- /dev/null
+++ b/ice/mandelbrot/source/impl_1/renderer.sv
@@ -0,0 +1,82 @@
+module renderer
+#(
+	parameter ITERATIONS = 7,
+	parameter OUTPUT_WIDTH = 3,
+	localparam ITERATION_WIDTH = $clog2(ITERATIONS + 1),
+	localparam SHIFT_AMOUNT = ITERATION_WIDTH - OUTPUT_WIDTH
+)(
+	input wire clk,
+	input wire rst,
+	input wire start,
+	input wire signed [7:0] x,
+	input wire signed [7:0] y,
+	output reg done,
+	output reg [OUTPUT_WIDTH-1:0] iters
+);
+
+reg signed [7:0] x_reg;
+reg signed [7:0] y_reg;
+reg signed [7:0] z_real;
+reg signed [7:0] z_imag;
+reg [ITERATION_WIDTH-1:0] current_iteration;
+
+wire signed [15:0] a_squared_p;
+wire signed [15:0] b_squared_p;
+wire signed [15:0] ab_p;
+
+wire signed [7:0] a_squared;
+wire signed [7:0] b_squared;
+wire signed [7:0] ab;
+
+always_ff @(posedge clk) begin
+	current_iteration <= current_iteration + 1'b1;
+	done <= 1'b0;
+	
+	// 128 = 4 << FRACTION_BITS (4)
+	if (current_iteration == ITERATIONS || a_squared + b_squared >= 32) begin
+		x_reg <= '0;
+		y_reg <= '0;
+		
+		z_real <= '0;
+		z_imag <= '0;
+		
+		iters <= current_iteration >> SHIFT_AMOUNT;
+		current_iteration <= '0;
+		
+		done <= 1'b1;
+	end else if (current_iteration == 0) begin
+		// store c for later
+		x_reg <= x;
+		y_reg <= y;
+		
+		// add c for first iteration.
+		// no need to include z as it is initially (0, 0)
+		z_real <= x;
+		z_imag <= y;
+		
+		if (!start) begin
+			current_iteration <= '0;
+		end
+	end else begin
+		z_real <= a_squared + b_squared + x_reg;
+		z_imag <= (ab << 1'b1) + y_reg;
+	end
+	
+	if (rst) begin
+		x_reg <= 8'h00;
+		y_reg <= 8'h00;
+		z_real <= 8'h00;
+		z_imag <= 8'h00;
+		current_iteration <= '0;
+	end
+end
+
+multiplier m1(.clk(clk), .a(z_real), .b(z_real), .product(a_squared_p));
+multiplier m2(.clk(clk), .a(z_imag), .b(z_imag), .product(b_squared_p));
+multiplier m3(.clk(clk), .a(z_real), .b(z_imag), .product(ab_p));
+
+assign a_squared = a_squared_p[11:4];
+assign b_squared = b_squared_p[11:4];
+assign ab = ab_p[11:4];
+
+endmodule
\ No newline at end of file
diff --git a/ice/mandelbrot/source/impl_1/tb_top.cpp b/ice/mandelbrot/source/impl_1/tb_top.cpp
new file mode 100644
index 0000000..2f655e3
--- /dev/null
+++ b/ice/mandelbrot/source/impl_1/tb_top.cpp
@@ -0,0 +1,32 @@
+#include <cstdlib>
+#include <iostream>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include "Vtop.h"
+
+constexpr vluint64_t MAX_SIM_TIME = 100000;
+vluint64_t sim_time = 0;
+
+int main(int argc, char** argv, char** env)
+{
+	Vtop* dut = new Vtop;
+
+	Verilated::traceEverOn(true);
+	VerilatedVcdC* m_trace = new VerilatedVcdC;
+	dut->trace(m_trace, 5);
+	m_trace->open("waveform.vcd");
+
+	while (sim_time < MAX_SIM_TIME)
+	{
+		dut->clk ^= 1;
+		dut->eval();
+		m_trace->dump(sim_time);
+
+		sim_time++;
+	}
+
+	m_trace->close();
+	delete m_trace;
+	delete dut;
+	return EXIT_SUCCESS;
+}
diff --git a/ice/mandelbrot/source/impl_1/top.sv b/ice/mandelbrot/source/impl_1/top.sv
index 3c35b81..f4319ce 100644
--- a/ice/mandelbrot/source/impl_1/top.sv
+++ b/ice/mandelbrot/source/impl_1/top.sv
@@ -7,35 +7,44 @@ module top
 	inout wire [7:0] data
 );
 
+reg [3:0] clk_div_8_counter;
+wire clk_div_8;
+
 reg dir_last;
 reg req_last;
 
 reg req_r;
-reg fin_r;
-reg [7:0] data_r;
-
-reg [6:0] x;
-reg [6:0] y;
-
-reg cntr;
 
 reg [7:0] waddr;
 reg [7:0] raddr;
 
 wire [7:0] command;
 
-RAM command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
+ram command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
+
+wire [6:0] x[4];
+wire [6:0] y[4];
+
+coords #(.POS_COUNT(4)) coords_inst(.clk(clk_div_8), .rst(!req_r), .x(x), .y(y), .finished(fin));
+
+wire [2:0] iters[4];
+
+wire [7:0] data_out;
+
+genvar i;
+generate
+	for (i = 0; i < 4; i = i + 1) begin
+		renderer r(.clk(clk), .rst(dir), .start(clk_div_8_counter[2:0] >> 1 == i), .x({x[i], 1'b0}), .y({y[i], 1'b0}), .done(), .iters(iters[i]));
+	end
+endgenerate
 
 always_ff @(posedge clk) begin
 	dir_last <= dir;
 	req_last <= req;
-	req_r <= !fin_r && !dir_last;
+	req_r <= !fin && !dir_last;
 	
 	if (dir) begin
-		x <= 0;
-		y <= 0;
-		fin_r <= 0;
-		cntr <= 0;
+		clk_div_8_counter <= 0;
 		raddr <= 0;
 		
 		if (req && req_last) begin
@@ -43,33 +52,18 @@ always_ff @(posedge clk) begin
 		end else begin
 			waddr <= 0;
 		end
-	end else begin
-		cntr <= !cntr;
-		if (cntr) begin
-			data_r <= command;
-			raddr <= 1 - raddr;
-			if (x + y == 0) begin
-				fin_r <= 1;
-			end
-		end else begin
-			data_r <= ((x + y) >> 1) + 16;
-			
-			if (x < 127) begin
-				x <= x + 1;
-			end else begin
-				x <= 0;
-				if (y < 127) begin
-					y <= y + 1;
-				end else begin
-					y <= 0;
-				end
-			end
-		end
+	end
+	
+	if (!dir && !dir_last) begin
+		clk_div_8_counter <= clk_div_8_counter + 1;
 	end
 end
 
+assign clk_div_8 = clk_div_8_counter[3];
+
+assign data_out = clk_div_8_counter[0] ? 128 : ((8'(iters[clk_div_8_counter[2:1]]) << 4) + 8'd62);
+
 assign req = dir ? 'Z : req_r;
-assign fin = fin_r;
-assign data = dir ? 'Z : data_r;
+assign data = dir ? 'Z : data_out;
 
 endmodule
\ No newline at end of file
diff --git a/ice/ram.sv b/ice/ram.sv
index c97cb2c..b233ece 100644
--- a/ice/ram.sv
+++ b/ice/ram.sv
@@ -1,4 +1,4 @@
-module RAM
+module ram
 #(
 	parameter ADDR_WIDTH = 8,
 	parameter DATA_WIDTH = 8
diff --git a/ice/top.sv b/ice/top.sv
deleted file mode 100644
index 541fb26..0000000
--- a/ice/top.sv
+++ /dev/null
@@ -1,8 +0,0 @@
-module top
-(
-	input wire clk,
-	input wire start,
-	output wire [7:0] data
-);
-
-endmodule
\ No newline at end of file