module spram_big
(
	input wire clk,
	input wire [3:0] we[4],
	input wire [15:0] addr,
	input wire [15:0] data_in[4],
	output wire [15:0] data_out
);

wire [15:0] datas_out[4];

genvar i;
generate
	for (i = 0; i < 4; i = i + 1) begin
		spram spram_inst(.clk(clk), .we(we[i]), .addr(addr[15:2]), .data_in(data_in[i]), .data_out(datas_out[i]));
	end
endgenerate

assign data_out = datas_out[addr[1:0]];

endmodule