module top
(
	input wire clk,
	input wire start,
	output wire [7:0] data
);

reg [7:0] data_r;

always_ff @(posedge clk) begin
	data_r <= data_r + 1;
	
	if (data_r < 16 || data_r > 235) begin
		data_r <= 16;
	end
end

assign data = data_r;

endmodule