module top
(
	input wire clk,
	input wire dir,
	inout wire req,
	output wire fin,
	inout wire [7:0] data
);

reg [3:0] clk_div_8_counter;
wire clk_div_8;

reg dir_last;
reg req_last;

reg req_r;

reg [7:0] waddr;
reg [7:0] raddr;

wire [7:0] command;

ram command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));

wire [6:0] x[4];
wire [6:0] y[4];

coords #(.POS_COUNT(4)) coords_inst(.clk(clk_div_8), .rst(!req_r), .x(x), .y(y), .finished(fin));

wire [2:0] iters[4];

wire [7:0] data_out;

genvar i;
generate
	for (i = 0; i < 4; i = i + 1) begin
		renderer r(.clk(clk), .rst(dir), .start(clk_div_8_counter[2:0] >> 1 == i), .x({x[i], 1'b0}), .y({y[i], 1'b0}), .done(), .iters(iters[i]));
	end
endgenerate

always_ff @(posedge clk) begin
	dir_last <= dir;
	req_last <= req;
	req_r <= !fin && !dir_last;
	
	if (dir) begin
		clk_div_8_counter <= 0;
		raddr <= 0;
		
		if (req && req_last) begin
			waddr <= waddr + 1;
		end else begin
			waddr <= 0;
		end
	end
	
	if (!dir && !dir_last) begin
		clk_div_8_counter <= clk_div_8_counter + 1;
	end
end

assign clk_div_8 = clk_div_8_counter[3];

assign data_out = clk_div_8_counter[0] ? 128 : ((8'(iters[clk_div_8_counter[2:1]]) << 4) + 8'd62);

assign req = dir ? 'Z : req_r;
assign data = dir ? 'Z : data_out;

endmodule