.pio_version 0

.program fpga
.fifo rx

set x, 8

.wrap_target

in x, 4
in null, 4
push

in pins, 8 [1]
push

in x, 4
in null, 4
push

in pins, 8 [1]
push

.wrap

% c-sdk {
#include <hardware/dma.h>

#ifndef DMA_CHANNEL
#define DMA_CHANNEL 0
#endif//DMA_CHANNEL

static uint8_t frame_buffer[2][FRAME_WIDTH * FRAME_HEIGHT * 16 / 8] = { };
static bool current_frame = false;

static inline void fpga_program_init(PIO pio, uint sm, uint offset, uint pin_base, float div)
{
    {
        pio_sm_config c = fpga_program_get_default_config(offset);
        sm_config_set_in_pins(&c, pin_base);
        pio_sm_set_consecutive_pindirs(pio, sm, pin_base, 8, false);

        sm_config_set_in_shift(&c, false, false, 8);

        pio_sm_init(pio, sm, offset, &c);
    }
    {
        dma_channel_config c = dma_channel_get_default_config(DMA_CHANNEL);
        channel_config_set_read_increment(&c, false);
        channel_config_set_write_increment(&c, true);
        channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
        channel_config_set_dreq(&c, pio_get_dreq(pio, sm, false));

        dma_channel_configure(DMA_CHANNEL, &c, NULL, &pio->rxf[sm], FRAME_WIDTH * FRAME_HEIGHT * 2 + 1, false);
    }
}
%}