43 lines
892 B
Systemverilog
43 lines
892 B
Systemverilog
module coords
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#(
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parameter WIDTH = 256,
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parameter HEIGHT = 256,
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parameter POS_COUNT = 4,
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localparam WIDTH_BITS = $clog2(WIDTH),
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localparam HEIGHT_BITS = $clog2(HEIGHT)
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)(
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input wire clk,
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input wire rst,
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input wire inc,
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output reg [WIDTH_BITS-1:0] x[POS_COUNT],
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output reg [HEIGHT_BITS-1:0] y[POS_COUNT],
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output wire finished
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);
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reg [POS_COUNT-1:0] finished_r;
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always_ff @(posedge clk) begin
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if (rst) begin
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integer i;
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for (i = 0; i < POS_COUNT; i = i + 1) begin
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x[i] <= WIDTH_BITS'(i);
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y[i] <= 0;
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end
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finished_r <= '1;
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end else if (inc) begin
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integer i;
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for (i = 0; i < POS_COUNT; i = i + 1) begin
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x[i] <= x[i] + POS_COUNT;
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if (32'(x[i]) > (32'(x[i]) + POS_COUNT) % WIDTH) begin
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y[i] <= y[i] + 1;
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if (32'(y[i]) > (32'(y[i]) + 1) % HEIGHT) begin
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finished_r[i] <= 0;
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end
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end
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end
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end
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end
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assign finished = finished_r == 0;
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endmodule |