99 lines
2.3 KiB
Systemverilog
99 lines
2.3 KiB
Systemverilog
module renderer
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#(
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parameter ITERATIONS = 127,
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parameter OUTPUT_WIDTH = 7,
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localparam ITERATION_WIDTH = $clog2(ITERATIONS + 1),
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localparam SHIFT_AMOUNT = ITERATION_WIDTH - OUTPUT_WIDTH,
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localparam FRACTION_BITS = 13
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)(
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input wire clk,
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input wire rst,
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input wire start,
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input wire [7:0] x,
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input wire [7:0] y,
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input wire signed [14:0] cx,
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input wire signed [14:0] cy,
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input wire [2:0] zoom,
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output reg done,
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output reg [OUTPUT_WIDTH-1:0] iters
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);
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reg signed [15:0] x_reg;
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reg signed [15:0] y_reg;
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reg signed [15:0] z_real;
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reg signed [15:0] z_imag;
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reg [ITERATION_WIDTH-1:0] current_iteration;
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wire signed [31:0] a_squared_p;
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wire signed [31:0] b_squared_p;
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wire signed [31:0] ab_p;
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wire signed [31:0] apb_squared;
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wire signed [31:0] asb_squared;
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wire signed [31:0] ab;
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always_ff @(posedge clk) begin
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done <= 1'b0;
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if (current_iteration == ITERATIONS) begin
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x_reg <= '0;
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y_reg <= '0;
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z_real <= '0;
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z_imag <= '0;
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current_iteration <= '0;
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iters <= '0;
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done <= 1'b1;
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end else if (apb_squared >= 32'h4 << (2 * FRACTION_BITS)) begin
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x_reg <= '0;
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y_reg <= '0;
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z_real <= '0;
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z_imag <= '0;
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current_iteration <= '0;
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iters <= OUTPUT_WIDTH'(current_iteration >> SHIFT_AMOUNT);
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done <= 1'b1;
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end else if (current_iteration == 0) begin
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// store c for later
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x_reg <= cx + (16'(x) << zoom) + 16'hC000;
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y_reg <= cy + (16'(y) << zoom) + 16'hC000;
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// add c for first iteration.
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// no need to include z as it is initially (0, 0)
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z_real <= cx + (16'(x) << zoom) + 16'hC000;
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z_imag <= cy + (16'(y) << zoom) + 16'hC000;
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if (!start) begin
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current_iteration <= '0;
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end else begin
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current_iteration <= current_iteration + 1'b1;
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end
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end else begin
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z_real <= asb_squared[15+FRACTION_BITS:FRACTION_BITS] + x_reg;
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z_imag <= ab[15+FRACTION_BITS:FRACTION_BITS] + y_reg;
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current_iteration <= current_iteration + 1'b1;
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end
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if (rst) begin
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x_reg <= '0;
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y_reg <= '0;
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z_real <= '0;
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z_imag <= '0;
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current_iteration <= '0;
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end
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end
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multiplier m1(.clk(clk), .a(z_real), .b(z_real), .product(a_squared_p));
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multiplier m2(.clk(clk), .a(z_imag), .b(z_imag), .product(b_squared_p));
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multiplier m3(.clk(clk), .a(z_real), .b(z_imag), .product(ab_p));
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assign apb_squared = a_squared_p + b_squared_p;
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assign asb_squared = a_squared_p - b_squared_p;
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assign ab = ab_p << 1'b1;
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endmodule |