80 lines
1.7 KiB
Systemverilog
80 lines
1.7 KiB
Systemverilog
module top
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(
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input wire clk,
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input wire dir,
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inout wire req,
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output wire fin,
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inout wire [7:0] data
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);
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reg req_last;
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reg [7:0] waddr;
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reg [7:0] raddr;
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wire [7:0] command;
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ram command_buffer(.wclk(clk), .rclk(clk), .waddr(waddr), .raddr(raddr), .data_in(data), .write_en(dir && req), .data_out(command));
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wire [6:0] iters;
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wire [7:0] x[1];
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wire [7:0] y[1];
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wire coords_fin;
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wire coords_inc;
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reg coords_inc_last;
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reg coords_fin_last;
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renderer r(.clk(clk), .rst(dir), .start(!dir && !coords_fin), .x(x[0]), .y(y[0]), .cx(16'h1000), .cy(16'h2000), .zoom(3'd6), .done(coords_inc), .iters(iters));
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coords #(.POS_COUNT(1)) coords_inst(.clk(clk), .rst(dir), .inc(coords_inc), .x(x), .y(y), .finished(coords_fin));
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wire fb_clk;
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reg [15:0] fb_addr;
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wire fb_we;
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wire [15:0] fb_data_out;
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reg fb_half_out;
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spram_big fb(.clk(fb_clk), .we({ fb_we, fb_we, fb_we, fb_we }), .addr(fb_addr), .data_in({ 8'd128, 8'(iters) + 8'd62 }), .data_out(fb_data_out));
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always_ff @(posedge clk) begin
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req_last <= req;
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coords_fin_last <= coords_fin && !dir;
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coords_inc_last <= coords_inc && !dir;
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if (dir) begin
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raddr <= 0;
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fb_addr <= 0;
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fb_half_out <= 0;
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if (req && req_last) begin
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waddr <= waddr + 1;
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end else begin
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waddr <= 0;
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end
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end else if (coords_fin) begin
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if (!coords_fin_last) begin
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fb_addr <= 0;
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fb_half_out <= 0;
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end else begin
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fb_half_out <= !fb_half_out;
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if (fb_half_out) begin
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fb_addr <= fb_addr + 1;
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end
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end
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end else if (coords_inc_last) begin
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fb_addr <= fb_addr + 1;
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end
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end
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assign fb_clk = clk;
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assign fb_we = coords_inc;
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assign fin = !dir && coords_fin && coords_fin_last && fb_addr >= 65531;
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assign req = dir ? 'Z : coords_fin_last;
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assign data = dir ? 'Z : (fb_half_out ? fb_data_out[15:8] : fb_data_out[7:0]);
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endmodule |