module top
(
	input wire clk,
	output wire led_r,
	output wire led_g,
	output wire led_b,
	output wire [7:0] data
);

localparam N = 25;

reg [N:0] counter;

always_ff @(posedge clk) begin
	counter <= counter + 1;
end

assign led_r = 1'b1;
assign led_g = counter[N];
assign led_b = 1'b1;

assign data = '0;

endmodule