18 lines
1.0 KiB
XML
18 lines
1.0 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<RadiantProject version="4.2" radiant="2024.2.0.3.0" title="mandelbrot" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" family_int="ice40tp" device_int="itpa08" package_int="SG48" operation_int="IND" speed_int="6" default_implementation="impl_1">
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<Options/>
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<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="synplify" default_strategy="Strategy1">
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<Options VerilogStandard="System Verilog" top="top"/>
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<Source name="source/impl_1/top.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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</Source>
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<Source name="source/impl_1/impl_1.pdc" type="Physical Constraints File" type_short="PDC">
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<Options/>
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</Source>
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<Source name="source/impl_1/impl_1.sdc" type="Pre-Synthesis Constraints File" type_short="SDC">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="mandelbrot1.sty"/>
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</RadiantProject>
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