21 lines
293 B
Systemverilog
21 lines
293 B
Systemverilog
module top
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(
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input wire clk,
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output wire led_r,
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output wire led_g,
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output wire led_b
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);
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localparam N = 22;
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reg [N:0] counter;
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always_ff @(posedge clk) begin
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counter <= counter + 1;
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end
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assign led_r = 1'b1;
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assign led_g = counter[N];
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assign led_b = 1'b1;
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endmodule |