34 lines
596 B
Systemverilog
34 lines
596 B
Systemverilog
`timescale 1ps / 1ps
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module spi(
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input wire nreset,
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input wire clk,
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input wire [7:0] data,
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input wire send_data,
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output wire sck,
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output wire mosi,
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output wire next
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);
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logic [2:0] current_bit;
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always_ff @(posedge clk) begin
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if (send_data == 1) begin
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current_bit <= current_bit + 1;
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if (current_bit == 3'b111) begin
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current_bit <= '0;
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end
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end
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if (nreset == 1'b0) begin
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current_bit <= '0;
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end
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end
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assign mosi = send_data == 1 ? data[7 - current_bit] : 0;
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assign next = current_bit == 3'b110; // one bit early to allow for a response in time
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assign sck = clk;
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endmodule
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