[CIR][AArch64] Upstream vmull_*/vmull_high_* and vmul_p8/vmul_high_p8 Neon builtins (#188371)
Add CIR generation for AArch64 NEON builtins `vmull_*` and `vmull_high_*` The accompanying tests from [AArch64/neon-instrinsics](https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/AArch64/neon-intrinsics.c) were integrated with new checks for CIR codegen. Part of #185382
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@ -397,6 +397,43 @@ public:
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}
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bool isInt(mlir::Type i) { return mlir::isa<cir::IntType>(i); }
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cir::IntType getExtendedIntTy(cir::IntType ty, bool isSigned) {
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switch (ty.getWidth()) {
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case 8:
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return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty;
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case 16:
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return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty;
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case 32:
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return isSigned ? typeCache.sInt64Ty : typeCache.uInt64Ty;
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default:
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llvm_unreachable("NYI");
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}
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}
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cir::IntType getTruncatedIntTy(cir::IntType ty, bool isSigned) {
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switch (ty.getWidth()) {
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case 16:
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return isSigned ? typeCache.sInt8Ty : typeCache.uInt8Ty;
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case 32:
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return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty;
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case 64:
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return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty;
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default:
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llvm_unreachable("NYI");
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}
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}
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cir::VectorType
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getExtendedOrTruncatedElementVectorType(cir::VectorType vt, bool isExtended,
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bool isSigned = false) {
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auto elementTy = mlir::dyn_cast_or_null<cir::IntType>(vt.getElementType());
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assert(elementTy && "expected int vector");
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return cir::VectorType::get(isExtended
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? getExtendedIntTy(elementTy, isSigned)
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: getTruncatedIntTy(elementTy, isSigned),
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vt.getSize());
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}
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// Fetch the type representing a pointer to unsigned int8 values.
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cir::PointerType getUInt8PtrTy() { return typeCache.uInt8PtrTy; }
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@ -472,6 +472,14 @@ static mlir::Value emitCommonNeonBuiltinExpr(
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case NEON::BI__builtin_neon_vfmlslq_high_f16:
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case NEON::BI__builtin_neon_vmmlaq_s32:
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case NEON::BI__builtin_neon_vmmlaq_u32:
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cgf.cgm.errorNYI(expr->getSourceRange(),
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std::string("unimplemented AArch64 builtin call: ") +
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ctx.BuiltinInfo.getName(builtinID));
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return mlir::Value{};
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case NEON::BI__builtin_neon_vmul_v:
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case NEON::BI__builtin_neon_vmulq_v:
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return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy,
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ops);
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case NEON::BI__builtin_neon_vusmmlaq_s32:
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case NEON::BI__builtin_neon_vusdot_s32:
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case NEON::BI__builtin_neon_vusdotq_s32:
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@ -2229,11 +2237,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
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case NEON::BI__builtin_neon_vfmas_laneq_f32:
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case NEON::BI__builtin_neon_vfmad_lane_f64:
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case NEON::BI__builtin_neon_vfmad_laneq_f64:
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case NEON::BI__builtin_neon_vmull_v:
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cgm.errorNYI(expr->getSourceRange(),
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std::string("unimplemented AArch64 builtin call: ") +
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getContext().BuiltinInfo.getName(builtinID));
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return mlir::Value{};
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case NEON::BI__builtin_neon_vmull_v: {
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intrName = usgn ? "aarch64.neon.umull" : "aarch64.neon.smull";
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if (type.isPoly())
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intrName = "aarch64.neon.pmull";
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cir::VectorType argTy = builder.getExtendedOrTruncatedElementVectorType(
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ty, /*isExtended*/ false, !usgn);
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return emitNeonCall(cgm, builder, {argTy, argTy}, ops, intrName, ty, loc);
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}
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case NEON::BI__builtin_neon_vmax_v:
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case NEON::BI__builtin_neon_vmaxq_v:
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intrName = usgn ? "aarch64.neon.umax" : "aarch64.neon.smax";
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@ -539,26 +539,6 @@ float64x2_t test_vmulq_f64(float64x2_t v1, float64x2_t v2) {
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return vmulq_f64(v1, v2);
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}
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// CHECK-LABEL: define dso_local <8 x i8> @test_vmul_p8(
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// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]])
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// CHECK-NEXT: ret <8 x i8> [[VMUL_V_I]]
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//
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poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) {
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return vmul_p8(v1, v2);
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}
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// CHECK-LABEL: define dso_local <16 x i8> @test_vmulq_p8(
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// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]])
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// CHECK-NEXT: ret <16 x i8> [[VMULQ_V_I]]
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//
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poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) {
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return vmulq_p8(v1, v2);
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}
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// CHECK-LABEL: define dso_local <8 x i8> @test_vmla_s8(
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// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]], <8 x i8> noundef [[V3:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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@ -10830,170 +10810,6 @@ uint64x2_t test_vabal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c) {
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return vabal_high_u32(a, b, c);
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}
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// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_s8(
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// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
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// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]
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//
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int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) {
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return vmull_s8(a, b);
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}
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// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_s16(
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// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
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// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])
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// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]
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//
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int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) {
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return vmull_s16(a, b);
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}
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// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_s32(
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// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
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// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
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// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])
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// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]
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//
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int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) {
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return vmull_s32(a, b);
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}
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// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_u8(
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// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
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// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]
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//
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uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) {
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return vmull_u8(a, b);
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}
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// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_u16(
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// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
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// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])
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// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]
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//
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uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) {
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return vmull_u16(a, b);
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}
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// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_u32(
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// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
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// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
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// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])
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// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]
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//
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uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) {
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return vmull_u32(a, b);
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}
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// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_s8(
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// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]])
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// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]]
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//
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int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) {
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return vmull_high_s8(a, b);
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}
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// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_s16(
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// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
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// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])
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// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]
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//
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int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) {
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return vmull_high_s16(a, b);
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}
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// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_s32(
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// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
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// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
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// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
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// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])
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// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]
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//
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int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) {
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return vmull_high_s32(a, b);
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}
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// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_u8(
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// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]])
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// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]]
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//
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uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) {
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return vmull_high_u8(a, b);
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}
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// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_u16(
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// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8>
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// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8>
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// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
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// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])
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// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]
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//
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uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) {
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return vmull_high_u16(a, b);
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}
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// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_u32(
|
||||
// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: [[ENTRY:.*:]]
|
||||
// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
|
||||
// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8>
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8>
|
||||
// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
|
||||
// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
|
||||
// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])
|
||||
// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]
|
||||
//
|
||||
uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) {
|
||||
return vmull_high_u32(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define dso_local <8 x i16> @test_vmlal_s8(
|
||||
// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: [[ENTRY:.*:]]
|
||||
@ -11558,28 +11374,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) {
|
||||
return vqdmlsl_high_s32(a, b, c);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_p8(
|
||||
// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: [[ENTRY:.*:]]
|
||||
// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
|
||||
// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]
|
||||
//
|
||||
poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) {
|
||||
return vmull_p8(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_p8(
|
||||
// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: [[ENTRY:.*:]]
|
||||
// CHECK-NEXT: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]])
|
||||
// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]]
|
||||
//
|
||||
poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) {
|
||||
return vmull_high_p8(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define dso_local i64 @test_vaddd_s64(
|
||||
// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
|
||||
// CHECK-NEXT: [[ENTRY:.*:]]
|
||||
|
||||
@ -1275,3 +1275,246 @@ float64x2_t test_vmaxnmq_f64(float64x2_t v1, float64x2_t v2) {
|
||||
return vmaxnmq_f64(v1, v2);
|
||||
}
|
||||
|
||||
//===------------------------------------------------------===//
|
||||
// 2.1.1.2.8. Widening Multiplication
|
||||
//===------------------------------------------------------===//
|
||||
|
||||
// LLVM-LABEL: @test_vmull_s8(
|
||||
// CIR-LABEL: @vmull_s8(
|
||||
int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i>
|
||||
|
||||
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I]]
|
||||
return vmull_s8(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_s16(
|
||||
// CIR-LABEL: @vmull_s16(
|
||||
int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s32i>
|
||||
|
||||
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])
|
||||
// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]]
|
||||
return vmull_s16(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_s32(
|
||||
// CIR-LABEL: @vmull_s32(
|
||||
int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s64i>
|
||||
|
||||
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])
|
||||
// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]]
|
||||
return vmull_s32(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_u8(
|
||||
// CIR-LABEL: @vmull_u8(
|
||||
uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u16i>
|
||||
|
||||
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I]]
|
||||
return vmull_u8(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_u16(
|
||||
// CIR-LABEL: @vmull_u16(
|
||||
uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u32i>
|
||||
|
||||
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])
|
||||
// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]]
|
||||
return vmull_u16(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_u32(
|
||||
// CIR-LABEL: @vmull_u32(
|
||||
uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u64i>
|
||||
|
||||
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])
|
||||
// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]]
|
||||
return vmull_u32(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_s8(
|
||||
// CIR-LABEL: @vmull_high_s8(
|
||||
int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s8
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s8
|
||||
// CIR: cir.call @vmull_s8([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]]
|
||||
return vmull_high_s8(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_s16(
|
||||
// CIR-LABEL: @vmull_high_s16(
|
||||
int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s16
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s16
|
||||
// CIR: {{%.*}} = cir.call @vmull_s16([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])
|
||||
// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]]
|
||||
return vmull_high_s16(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_s32(
|
||||
// CIR-LABEL: @vmull_high_s32(
|
||||
int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s32
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s32
|
||||
// CIR: {{%.*}} = cir.call @vmull_s32([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
|
||||
// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])
|
||||
// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]]
|
||||
return vmull_high_s32(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_u8(
|
||||
// CIR-LABEL: @vmull_high_u8(
|
||||
uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u8
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u8
|
||||
// CIR: {{%.*}} = cir.call @vmull_u8([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]]
|
||||
return vmull_high_u8(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_u16(
|
||||
// CIR-LABEL: @vmull_high_u16(
|
||||
uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u16
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u16
|
||||
// CIR: {{%.*}} = cir.call @vmull_u16([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
|
||||
// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])
|
||||
// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]]
|
||||
return vmull_high_u16(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_u32(
|
||||
// CIR-LABEL: @vmull_high_u32(
|
||||
uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u32
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u32
|
||||
// CIR: {{%.*}} = cir.call @vmull_u32([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
|
||||
// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
|
||||
// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
|
||||
// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])
|
||||
// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]]
|
||||
return vmull_high_u32(a, b);
|
||||
}
|
||||
|
||||
//===------------------------------------------------------===//
|
||||
// 2.1.1.3.1. Polynomial Multiply
|
||||
//===------------------------------------------------------===//
|
||||
|
||||
// LLVM-LABEL: @test_vmul_p8(
|
||||
// CIR-LABEL: @vmul_p8(
|
||||
poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i>
|
||||
|
||||
// LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> {{.*}} [[V2:%.*]])
|
||||
// LLVM: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]])
|
||||
// LLVM-NEXT: ret <8 x i8> [[VMUL_V_I]]
|
||||
return vmul_p8(v1, v2);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmulq_p8(
|
||||
// CIR-LABEL: @vmulq_p8(
|
||||
poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i>
|
||||
|
||||
// LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> {{.*}} [[V2:%.*]])
|
||||
// LLVM: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]])
|
||||
// LLVM-NEXT: ret <16 x i8> [[VMULQ_V_I]]
|
||||
return vmulq_p8(v1, v2);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_p8(
|
||||
// CIR-LABEL: @vmull_p8(
|
||||
poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) {
|
||||
// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i>
|
||||
|
||||
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I]]
|
||||
return vmull_p8(a, b);
|
||||
}
|
||||
|
||||
// LLVM-LABEL: @test_vmull_high_p8(
|
||||
// CIR-LABEL: @vmull_high_p8(
|
||||
poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) {
|
||||
// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_p8
|
||||
// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_p8
|
||||
// CIR: {{%.*}} = cir.call @vmull_p8([[HIGH_A]], [[HIGH_B]])
|
||||
|
||||
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]])
|
||||
// LLVM: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]])
|
||||
// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]]
|
||||
return vmull_high_p8(a, b);
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user