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[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)

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The logic in RISCVMatInt would previously produce lui+addiw on RV64
whenever a 32-bit integer must be materialised and the Hi20 and Lo12
parts are non-zero. However, sometimes addi can be used equivalently
(whenever the sign extension behaviour of addiw would be a no-op). This
patch moves to using addiw only when necessary. Although there is
absolutely no advantage in terms of compressibility or performance, this
has the following advantages:
* It's more consistent with logic used elsewhere in the backend. For
instance, RISCVOptWInstrs will try to convert addiw to addi on the basis
it reduces test diffs vs RV32.
* This matches the lowering GCC does in its codegen path. Unlike LLVM,
GCC seems to have different expansion logic for the assembler vs
codegen. For codegen it will use lui+addi if possible, but expanding
`li` in the assembler will always produces lui+addiw as LLVM did prior
to this commit. As someone who has been looking at a lot of gcc vs clang
diffs lately, reducing unnecessary divergence is of at least some value.
* As the diff for fold-mem-offset.ll shows, we can fold memory offsets
in more cases when addi is used. Memory offset folding could be taught
to recognise when the addiw could be replaced with an addi, but that
seems unnecessary when we can simply change the logic in RISCVMatInt.

As pointed out by @topperc during review, making this change without
modifying RISCVOptWInstrs risks introducing some cases where we fail to
remove a sext.w that we removed before. I've incorporated a patch based
on a suggestion from Craig that avoids it, and also adds appropriate
RISCVOptWInstrs test cases.

The initial patch description noted that the main motivation was to
avoid unnecessary differences both for RV32/RV64 and when comparing GCC,
but noted that very occasionally we see a benefit from memory offset
folding kicking in when it didn't before. Looking at the dynamic
instruction count difference for SPEC benchmarks targeting rva22u64 and
it shows we actually get a meaningful
~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data
more closely, the codegen difference is in `LBM_performStreamCollideTRT`
which as a function accounts for ~98% for dynamically executed
instructions and the codegen diffs appear to be a knock-on effect of the
address merging reducing register pressure right from function entry
(for instance, we get a big reduction in dynamically executed loads in
that function).

Below is the icount data (rva22u64 -O3, no LTO):
```
Benchmark                Baseline            This PR   Diff (%)
============================================================
500.perlbench_r         174116601991    174115795810     -0.00%
502.gcc_r               218903280858    218903215788     -0.00%
505.mcf_r               131208029185    131207692803     -0.00%
508.namd_r              217497594322    217497594297     -0.00%
510.parest_r            289314486153    289313577652     -0.00%
511.povray_r             30640531048     30640765701      0.00%
519.lbm_r                95897914862     91712688050     -4.36%
520.omnetpp_r           134641549722    134867015683      0.17%
523.xalancbmk_r         281462762992    281432092673     -0.01%
525.x264_r              379776121941    379535558210     -0.06%
526.blender_r           659736022025    659738387343      0.00%
531.deepsjeng_r         349122867552    349122867481     -0.00%
538.imagick_r           238558760552    238558753269     -0.00%
541.leela_r             406578560612    406385135260     -0.05%
544.nab_r               400997131674    400996765827     -0.00%
557.xz_r                130079522194    129945515709     -0.10%

```

The instcounting setup I use doesn't have good support for drilling down
into functions from outside the linked executable (e.g. libc). The
difference in omnetpp all seems to come from there, and does not reflect
any degradation in codegen quality.

I can confirm with the current version of the PR there is no change in
the number of static sext.w across all the SPEC 2017 benchmarks
(rva22u64 O3)

Co-authored-by: Craig Topper <craig.topper@sifive.com>
This commit is contained in:
Alex Bradbury 2025-06-02 22:24:50 +01:00 committed by GitHub
parent d313c09b28
commit 3d2650bdeb
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
153 changed files with 1926 additions and 1985 deletions
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10
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
View File

@ -94,7 +94,15 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
Res.emplace_back(RISCV::LUI, Hi20);
if (Lo12 || Hi20 == 0) {
unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
unsigned AddiOpc = RISCV::ADDI;
if (IsRV64 && Hi20) {
// Use ADDIW rather than ADDI only when necessary for correctness. As
// noted in RISCVOptWInstrs, this helps reduce test differences vs
// RV32 without being a pessimization.
int64_t LuiRes = SignExtend64<32>(Hi20 << 12);
if (!isInt<32>(LuiRes + Lo12))
AddiOpc = RISCV::ADDIW;
}
Res.emplace_back(AddiOpc, Lo12);
}
return;

22
llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
View File

@ -591,6 +591,27 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
return false;
break;
case RISCV::ADDI: {
if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg().isVirtual()) {
if (MachineInstr *SrcMI = MRI.getVRegDef(MI->getOperand(1).getReg())) {
if (SrcMI->getOpcode() == RISCV::LUI &&
SrcMI->getOperand(1).isImm()) {
uint64_t Imm = SrcMI->getOperand(1).getImm();
Imm = SignExtend64<32>(Imm << 12);
Imm += (uint64_t)MI->getOperand(2).getImm();
if (isInt<32>(Imm))
continue;
}
}
}
if (hasAllWUsers(*MI, ST, MRI)) {
FixableDef.insert(MI);
break;
}
return false;
}
// With these opcode, we can "fix" them with the W-version
// if we know all users of the result only rely on bits 31:0
case RISCV::SLLI:
@ -598,7 +619,6 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
if (MI->getOperand(2).getImm() >= 32)
return false;
[[fallthrough]];
case RISCV::ADDI:
case RISCV::ADD:
case RISCV::LD:
case RISCV::LWU:

2
llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
View File

@ -468,7 +468,7 @@ define i64 @subi_i64(i64 %a) {
; RV64IM-LABEL: subi_i64:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: lui a1, 1048275
; RV64IM-NEXT: addiw a1, a1, -1548
; RV64IM-NEXT: addi a1, a1, -1548
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:

8
llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
View File

@ -174,8 +174,8 @@ define i24 @bitreverse_i24(i24 %x) {
; RV64-NEXT: slli a1, a0, 16
; RV64-NEXT: lui a2, 4096
; RV64-NEXT: lui a3, 1048335
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: addiw a3, a3, 240
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: addi a3, a3, 240
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: srli a0, a0, 16
; RV64-NEXT: or a0, a0, a1
@ -184,7 +184,7 @@ define i24 @bitreverse_i24(i24 %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: lui a3, 1047757
; RV64-NEXT: addiw a3, a3, -820
; RV64-NEXT: addi a3, a3, -820
; RV64-NEXT: srli a1, a1, 4
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: and a1, a3, a2
@ -192,7 +192,7 @@ define i24 @bitreverse_i24(i24 %x) {
; RV64-NEXT: slli a0, a0, 2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: lui a3, 1047211
; RV64-NEXT: addiw a3, a3, -1366
; RV64-NEXT: addi a3, a3, -1366
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: or a0, a1, a0

14
llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
View File

@ -25,7 +25,7 @@ define i32 @udiv_constant_no_add(i32 %a) nounwind {
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: lui a1, 205
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: mul a0, a0, a1
@ -62,7 +62,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 149797
; RV64IM-NEXT: slli a2, a0, 32
; RV64IM-NEXT: addiw a1, a1, -1755
; RV64IM-NEXT: addi a1, a1, -1755
; RV64IM-NEXT: srli a2, a2, 32
; RV64IM-NEXT: mul a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 32
@ -75,7 +75,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IMZB-LABEL: udiv_constant_add:
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: lui a1, 149797
; RV64IMZB-NEXT: addiw a1, a1, -1755
; RV64IMZB-NEXT: addi a1, a1, -1755
; RV64IMZB-NEXT: zext.w a2, a0
; RV64IMZB-NEXT: mul a1, a2, a1
; RV64IMZB-NEXT: srli a1, a1, 32
@ -286,7 +286,7 @@ define i16 @udiv16_constant_no_add(i16 %a) nounwind {
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 13
; RV64IM-NEXT: srli a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 18
; RV64IM-NEXT: ret
@ -295,7 +295,7 @@ define i16 @udiv16_constant_no_add(i16 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: zext.h a0, a0
; RV64IMZB-NEXT: lui a1, 13
; RV64IMZB-NEXT: addiw a1, a1, -819
; RV64IMZB-NEXT: addi a1, a1, -819
; RV64IMZB-NEXT: mul a0, a0, a1
; RV64IMZB-NEXT: srli a0, a0, 18
; RV64IMZB-NEXT: ret
@ -340,8 +340,8 @@ define i16 @udiv16_constant_add(i16 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 2
; RV64IM-NEXT: lui a2, 16
; RV64IM-NEXT: addiw a1, a1, 1171
; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: addi a1, a1, 1171
; RV64IM-NEXT: addi a2, a2, -1
; RV64IM-NEXT: and a3, a0, a2
; RV64IM-NEXT: mul a1, a3, a1
; RV64IM-NEXT: srli a1, a1, 16

2
llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
View File

@ -1002,7 +1002,7 @@ define i1 @fpclass(float %x) {
; RV64I-NEXT: lui a4, 2048
; RV64I-NEXT: lui a5, 520192
; RV64I-NEXT: srli a2, a2, 33
; RV64I-NEXT: addiw a6, a4, -1
; RV64I-NEXT: addi a6, a4, -1
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: subw a3, a2, a3
; RV64I-NEXT: sltu a3, a3, a6

4
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
View File

@ -159,8 +159,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 648
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 648
; CHECK-NEXT: $x10 = COPY [[ADDI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_CONSTANT i64 -2147483000
$x10 = COPY %0(s64)

23
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
View File

@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: half_imm
@ -10,19 +10,12 @@ legalized: true
regBankSelected: true
body: |
bb.1:
; RV32-LABEL: name: half_imm
; RV32: [[LUI:%[0-9]+]]:gpr = LUI 4
; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584
; RV32-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]]
; RV32-NEXT: $f10_h = COPY [[FMV_H_X]]
; RV32-NEXT: PseudoRET implicit $f10_h
;
; RV64-LABEL: name: half_imm
; RV64: [[LUI:%[0-9]+]]:gpr = LUI 4
; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 584
; RV64-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDIW]]
; RV64-NEXT: $f10_h = COPY [[FMV_H_X]]
; RV64-NEXT: PseudoRET implicit $f10_h
; CHECK-LABEL: name: half_imm
; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 4
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584
; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]]
; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:fprb(s16) = G_FCONSTANT half 0xH4248
$f10_h = COPY %0(s16)
PseudoRET implicit $f10_h

35
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant.mir
View File

@ -10,19 +10,12 @@ legalized: true
regBankSelected: true
body: |
bb.1:
; RV32-LABEL: name: float_imm
; RV32: [[LUI:%[0-9]+]]:gpr = LUI 263313
; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -37
; RV32-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]]
; RV32-NEXT: $f10_f = COPY [[FMV_W_X]]
; RV32-NEXT: PseudoRET implicit $f10_f
;
; RV64-LABEL: name: float_imm
; RV64: [[LUI:%[0-9]+]]:gpr = LUI 263313
; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -37
; RV64-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDIW]]
; RV64-NEXT: $f10_f = COPY [[FMV_W_X]]
; RV64-NEXT: PseudoRET implicit $f10_f
; CHECK-LABEL: name: float_imm
; CHECK: [[LUI:%[0-9]+]]:gpr = LUI 263313
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -37
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]]
; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:fprb(s32) = G_FCONSTANT float 0x400921FB60000000
$f10_f = COPY %0(s32)
PseudoRET implicit $f10_f
@ -109,14 +102,14 @@ body: |
;
; RV64-LABEL: name: double_imm
; RV64: [[LUI:%[0-9]+]]:gpr = LUI 512
; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 1169
; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDIW]], 15
; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], -299
; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI]], 14
; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091
; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI1]], 12
; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744
; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI2]]
; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 1169
; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 15
; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI]], -299
; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI1]], 14
; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091
; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI2]], 12
; RV64-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744
; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI3]]
; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]
; RV64-NEXT: PseudoRET implicit $f10_d
%0:fprb(s64) = G_FCONSTANT double 0x400921FB54442D18

48
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
View File

@ -40,9 +40,9 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: li a1, 32
@ -97,9 +97,9 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: li a1, 32
@ -162,9 +162,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: li a1, 32
@ -221,9 +221,9 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: beqz s0, .LBB3_2
; RV64I-NEXT: # %bb.1:
@ -292,9 +292,9 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: li a1, 32
@ -421,9 +421,9 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -464,9 +464,9 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -506,9 +506,9 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: beqz s0, .LBB8_2
; RV64I-NEXT: # %bb.1:
@ -562,9 +562,9 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: li a0, 0
@ -681,9 +681,9 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -737,9 +737,9 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
; RV64I-NEXT: sraiw a1, a0, 4
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -1127,7 +1127,7 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind {
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srliw a2, a0, 8
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 8
@ -1185,7 +1185,7 @@ define i64 @bswap_i64(i64 %a) {
; RV64I-NEXT: srli a4, a0, 40
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a4, a4, a3
; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: srli a4, a0, 24

8
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
View File

@ -141,7 +141,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
@ -151,7 +151,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: lui a2, 16
; RV64ZBKB-NEXT: zext.b a0, a0
; RV64ZBKB-NEXT: addiw a2, a2, -256
; RV64ZBKB-NEXT: addi a2, a2, -256
; RV64ZBKB-NEXT: slli a1, a1, 8
; RV64ZBKB-NEXT: and a1, a1, a2
; RV64ZBKB-NEXT: or a0, a1, a0
@ -189,7 +189,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a1, a0
@ -199,7 +199,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: lui a2, 16
; RV64ZBKB-NEXT: zext.b a0, a0
; RV64ZBKB-NEXT: addiw a2, a2, -256
; RV64ZBKB-NEXT: addi a2, a2, -256
; RV64ZBKB-NEXT: slli a1, a1, 8
; RV64ZBKB-NEXT: and a1, a1, a2
; RV64ZBKB-NEXT: or a0, a1, a0

16
llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
View File

@ -1171,7 +1171,7 @@ define void @va3_caller() nounwind {
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: lui a1, 5
; RV64-NEXT: li a0, 2
; RV64-NEXT: addiw a2, a1, -480
; RV64-NEXT: addi a2, a1, -480
; RV64-NEXT: li a1, 1111
; RV64-NEXT: call va3
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -1203,7 +1203,7 @@ define void @va3_caller() nounwind {
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: lui a1, 5
; RV64-WITHFP-NEXT: li a0, 2
; RV64-WITHFP-NEXT: addiw a2, a1, -480
; RV64-WITHFP-NEXT: addi a2, a1, -480
; RV64-WITHFP-NEXT: li a1, 1111
; RV64-WITHFP-NEXT: call va3
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -1618,7 +1618,7 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-LABEL: va_large_stack:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, 24414
; RV64-NEXT: addiw a0, a0, 336
; RV64-NEXT: addi a0, a0, 336
; RV64-NEXT: sub sp, sp, a0
; RV64-NEXT: .cfi_def_cfa_offset 100000080
; RV64-NEXT: lui a0, 24414
@ -1635,7 +1635,7 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: sd a4, 304(a0)
; RV64-NEXT: addi a0, sp, 8
; RV64-NEXT: lui a1, 24414
; RV64-NEXT: addiw a1, a1, 280
; RV64-NEXT: addi a1, a1, 280
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: sd a1, 8(sp)
; RV64-NEXT: lw a0, 4(a0)
@ -1657,7 +1657,7 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: sw a2, 12(sp)
; RV64-NEXT: lw a0, 0(a0)
; RV64-NEXT: lui a1, 24414
; RV64-NEXT: addiw a1, a1, 336
; RV64-NEXT: addi a1, a1, 336
; RV64-NEXT: add sp, sp, a1
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
@ -1714,10 +1714,10 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-WITHFP-NEXT: addi s0, sp, 1968
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 64
; RV64-WITHFP-NEXT: lui a0, 24414
; RV64-WITHFP-NEXT: addiw a0, a0, -1680
; RV64-WITHFP-NEXT: addi a0, a0, -1680
; RV64-WITHFP-NEXT: sub sp, sp, a0
; RV64-WITHFP-NEXT: lui a0, 24414
; RV64-WITHFP-NEXT: addiw a0, a0, 288
; RV64-WITHFP-NEXT: addi a0, a0, 288
; RV64-WITHFP-NEXT: sub a0, s0, a0
; RV64-WITHFP-NEXT: sd a1, 8(s0)
; RV64-WITHFP-NEXT: sd a2, 16(s0)
@ -1738,7 +1738,7 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-WITHFP-NEXT: sw a3, 4(a0)
; RV64-WITHFP-NEXT: lw a0, 0(a1)
; RV64-WITHFP-NEXT: lui a1, 24414
; RV64-WITHFP-NEXT: addiw a1, a1, -1680
; RV64-WITHFP-NEXT: addi a1, a1, -1680
; RV64-WITHFP-NEXT: add sp, sp, a1
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 2032
; RV64-WITHFP-NEXT: ld ra, 1960(sp) # 8-byte Folded Reload

102
llvm/test/CodeGen/RISCV/abdu-neg.ll
View File

@ -167,7 +167,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_ext_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sub a0, a0, a1
@ -271,7 +271,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_ext_i16_undef:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sub a0, a0, a1
@ -1125,45 +1125,25 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: abd_minmax_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: bgeu a0, a1, .LBB14_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: bgeu a1, a0, .LBB14_4
; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: sub a0, a2, a0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB14_3:
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu a1, a0, .LBB14_2
; RV32I-NEXT: .LBB14_4:
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_minmax_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: bgeu a0, a1, .LBB14_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bgeu a1, a0, .LBB14_4
; RV64I-NEXT: .LBB14_2:
; RV64I-NEXT: sub a0, a2, a0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB14_3:
; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu a1, a0, .LBB14_2
; RV64I-NEXT: .LBB14_4:
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
; NOZBB-LABEL: abd_minmax_i16:
; NOZBB: # %bb.0:
; NOZBB-NEXT: lui a2, 16
; NOZBB-NEXT: addi a2, a2, -1
; NOZBB-NEXT: and a1, a1, a2
; NOZBB-NEXT: and a0, a0, a2
; NOZBB-NEXT: mv a2, a0
; NOZBB-NEXT: bgeu a0, a1, .LBB14_3
; NOZBB-NEXT: # %bb.1:
; NOZBB-NEXT: bgeu a1, a0, .LBB14_4
; NOZBB-NEXT: .LBB14_2:
; NOZBB-NEXT: sub a0, a2, a0
; NOZBB-NEXT: ret
; NOZBB-NEXT: .LBB14_3:
; NOZBB-NEXT: mv a2, a1
; NOZBB-NEXT: bltu a1, a0, .LBB14_2
; NOZBB-NEXT: .LBB14_4:
; NOZBB-NEXT: sub a0, a2, a1
; NOZBB-NEXT: ret
;
; ZBB-LABEL: abd_minmax_i16:
; ZBB: # %bb.0:
@ -1628,33 +1608,19 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: abd_cmp_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a3, a1, a2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: bltu a2, a3, .LBB19_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: abd_cmp_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a3, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: bltu a2, a3, .LBB19_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret
; NOZBB-LABEL: abd_cmp_i16:
; NOZBB: # %bb.0:
; NOZBB-NEXT: lui a2, 16
; NOZBB-NEXT: addi a2, a2, -1
; NOZBB-NEXT: and a3, a1, a2
; NOZBB-NEXT: and a2, a0, a2
; NOZBB-NEXT: bltu a2, a3, .LBB19_2
; NOZBB-NEXT: # %bb.1:
; NOZBB-NEXT: sub a0, a1, a0
; NOZBB-NEXT: ret
; NOZBB-NEXT: .LBB19_2:
; NOZBB-NEXT: sub a0, a0, a1
; NOZBB-NEXT: ret
;
; ZBB-LABEL: abd_cmp_i16:
; ZBB: # %bb.0:

10
llvm/test/CodeGen/RISCV/abdu.ll
View File

@ -137,7 +137,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_ext_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a0, a1
@ -228,7 +228,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_ext_i16_undef:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a0, a1
@ -992,7 +992,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_minmax_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a0, a1
@ -1382,7 +1382,7 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_cmp_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a0, a1
@ -1776,7 +1776,7 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: abd_select_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sub a0, a0, a1

10
llvm/test/CodeGen/RISCV/addimm-mulimm.ll
View File

@ -153,7 +153,7 @@ define i64 @add_mul_combine_accept_b3(i64 %x) {
; RV64IMB-NEXT: slli a0, a0, 5
; RV64IMB-NEXT: sub a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: addi a1, a1, 1119
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 8953
@ -685,7 +685,7 @@ define i64 @mul3000_add8990_c(i64 %x) {
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, -10
; RV64IMB-NEXT: ret
@ -761,7 +761,7 @@ define i64 @mul3000_sub8990_c(i64 %x) {
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, 10
; RV64IMB-NEXT: ret
@ -837,7 +837,7 @@ define i64 @mulneg3000_add8990_c(i64 %x) {
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, -10
; RV64IMB-NEXT: ret
@ -914,7 +914,7 @@ define i64 @mulneg3000_sub8990_c(i64 %x) {
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addi a0, a0, 10
; RV64IMB-NEXT: ret

2
llvm/test/CodeGen/RISCV/alu16.ll
View File

@ -286,7 +286,7 @@ define i16 @sltu(i16 %a, i16 %b) nounwind {
; RV64I-LABEL: sltu:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sltu a0, a0, a1

30
llvm/test/CodeGen/RISCV/atomic-rmw.ll
View File

@ -11018,7 +11018,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: li a2, 0
; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -11102,7 +11102,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: li a2, 2
; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -11208,7 +11208,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -11314,7 +11314,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: li a2, 4
; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -11420,7 +11420,7 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: li a2, 5
; RV64I-NEXT: call __atomic_exchange_2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@ -17923,7 +17923,7 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB120_2
; RV64I-NEXT: .LBB120_1: # %atomicrmw.start
@ -18125,7 +18125,7 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB121_2
; RV64I-NEXT: .LBB121_1: # %atomicrmw.start
@ -18377,7 +18377,7 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB122_2
; RV64I-NEXT: .LBB122_1: # %atomicrmw.start
@ -18629,7 +18629,7 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB123_2
; RV64I-NEXT: .LBB123_1: # %atomicrmw.start
@ -18856,7 +18856,7 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB124_2
; RV64I-NEXT: .LBB124_1: # %atomicrmw.start
@ -19033,7 +19033,7 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB125_2
; RV64I-NEXT: .LBB125_1: # %atomicrmw.start
@ -19235,7 +19235,7 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB126_2
; RV64I-NEXT: .LBB126_1: # %atomicrmw.start
@ -19487,7 +19487,7 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB127_2
; RV64I-NEXT: .LBB127_1: # %atomicrmw.start
@ -19739,7 +19739,7 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB128_2
; RV64I-NEXT: .LBB128_1: # %atomicrmw.start
@ -19966,7 +19966,7 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB129_2
; RV64I-NEXT: .LBB129_1: # %atomicrmw.start

4
llvm/test/CodeGen/RISCV/atomic-signext.ll
View File

@ -2023,7 +2023,7 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB23_2
; RV64I-NEXT: .LBB23_1: # %atomicrmw.start
@ -2171,7 +2171,7 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB24_2
; RV64I-NEXT: .LBB24_1: # %atomicrmw.start

8
llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
View File

@ -292,7 +292,7 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: .LBB1_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@ -331,7 +331,7 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
; RV64IA-NEXT: slli a5, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a0, a5, 24
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: lw a4, 0(a2)
; RV64IA-NEXT: sllw a5, a3, a5
; RV64IA-NEXT: not a5, a5
@ -955,7 +955,7 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: lui s1, 16
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: and s2, a1, s1
; RV64I-NEXT: .LBB5_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@ -992,7 +992,7 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; RV64IA-NEXT: slli a5, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a0, a5, 24
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: lw a4, 0(a2)
; RV64IA-NEXT: sllw a5, a3, a5
; RV64IA-NEXT: not a5, a5

8
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
View File

@ -274,7 +274,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: lui s1, 16
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: and s2, a1, s1
; RV64I-NEXT: .LBB1_1: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@ -311,7 +311,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; RV64IA-NEXT: slli a5, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a0, a5, 24
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: lw a4, 0(a2)
; RV64IA-NEXT: sllw a5, a3, a5
; RV64IA-NEXT: not a5, a5
@ -1001,7 +1001,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addiw s2, s2, -1
; RV64I-NEXT: addi s2, s2, -1
; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB5_2
; RV64I-NEXT: .LBB5_1: # %atomicrmw.start
@ -1048,7 +1048,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; RV64IA-NEXT: slli a5, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: andi a0, a5, 24
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: lw a4, 0(a2)
; RV64IA-NEXT: sllw a5, a3, a5
; RV64IA-NEXT: not a5, a5

4
llvm/test/CodeGen/RISCV/avgceilu.ll
View File

@ -75,7 +75,7 @@ define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {
; RV64I-LABEL: test_fixed_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
@ -104,7 +104,7 @@ define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {
; RV64I-LABEL: test_ext_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1

4
llvm/test/CodeGen/RISCV/avgflooru.ll
View File

@ -69,7 +69,7 @@ define i16 @test_fixed_i16(i16 %a0, i16 %a1) nounwind {
; RV64I-LABEL: test_fixed_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
@ -96,7 +96,7 @@ define i16 @test_ext_i16(i16 %a0, i16 %a1) nounwind {
; RV64I-LABEL: test_ext_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: add a0, a0, a1

56
llvm/test/CodeGen/RISCV/bittest.ll
View File

@ -271,19 +271,12 @@ define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind {
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_constant_by_var_shr_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: lui a1, 301408
; RV32ZBS-NEXT: addi a1, a1, 722
; RV32ZBS-NEXT: bext a0, a1, a0
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
; ZBS-LABEL: bittest_constant_by_var_shr_i32:
; ZBS: # %bb.0:
; ZBS-NEXT: lui a1, 301408
; ZBS-NEXT: addi a1, a1, 722
; ZBS-NEXT: bext a0, a1, a0
; ZBS-NEXT: ret
;
; RV32XTHEADBS-LABEL: bittest_constant_by_var_shr_i32:
; RV32XTHEADBS: # %bb.0:
@ -324,19 +317,12 @@ define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_constant_by_var_shl_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: lui a1, 301408
; RV32ZBS-NEXT: addi a1, a1, 722
; RV32ZBS-NEXT: bext a0, a1, a0
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
; ZBS-LABEL: bittest_constant_by_var_shl_i32:
; ZBS: # %bb.0:
; ZBS-NEXT: lui a1, 301408
; ZBS-NEXT: addi a1, a1, 722
; ZBS-NEXT: bext a0, a1, a0
; ZBS-NEXT: ret
;
; RV32XTHEADBS-LABEL: bittest_constant_by_var_shl_i32:
; RV32XTHEADBS: # %bb.0:
@ -374,7 +360,7 @@ define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
; RV64I-LABEL: bittest_constant_by_var_shr_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: addi a1, a1, 722
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
@ -382,14 +368,14 @@ define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: addi a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
;
; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i64:
; RV64XTHEADBS: # %bb.0:
; RV64XTHEADBS-NEXT: lui a1, 301408
; RV64XTHEADBS-NEXT: addiw a1, a1, 722
; RV64XTHEADBS-NEXT: addi a1, a1, 722
; RV64XTHEADBS-NEXT: srl a0, a1, a0
; RV64XTHEADBS-NEXT: andi a0, a0, 1
; RV64XTHEADBS-NEXT: ret
@ -414,7 +400,7 @@ define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
; RV64I-LABEL: bittest_constant_by_var_shl_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: addi a1, a1, 722
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
@ -422,14 +408,14 @@ define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: addi a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
;
; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i64:
; RV64XTHEADBS: # %bb.0:
; RV64XTHEADBS-NEXT: lui a1, 301408
; RV64XTHEADBS-NEXT: addiw a1, a1, 722
; RV64XTHEADBS-NEXT: addi a1, a1, 722
; RV64XTHEADBS-NEXT: srl a0, a1, a0
; RV64XTHEADBS-NEXT: andi a0, a0, 1
; RV64XTHEADBS-NEXT: ret
@ -462,7 +448,7 @@ define void @bittest_switch(i32 signext %0) {
; RV64I-NEXT: bltu a1, a0, .LBB14_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a1, 2048
; RV64I-NEXT: addiw a1, a1, 51
; RV64I-NEXT: addi a1, a1, 51
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
@ -492,7 +478,7 @@ define void @bittest_switch(i32 signext %0) {
; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3
; RV64ZBS-NEXT: # %bb.1:
; RV64ZBS-NEXT: lui a1, 2048
; RV64ZBS-NEXT: addiw a1, a1, 51
; RV64ZBS-NEXT: addi a1, a1, 51
; RV64ZBS-NEXT: slli a1, a1, 8
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: beqz a0, .LBB14_3
@ -522,7 +508,7 @@ define void @bittest_switch(i32 signext %0) {
; RV64XTHEADBS-NEXT: bltu a1, a0, .LBB14_3
; RV64XTHEADBS-NEXT: # %bb.1:
; RV64XTHEADBS-NEXT: lui a1, 2048
; RV64XTHEADBS-NEXT: addiw a1, a1, 51
; RV64XTHEADBS-NEXT: addi a1, a1, 51
; RV64XTHEADBS-NEXT: slli a1, a1, 8
; RV64XTHEADBS-NEXT: srl a0, a1, a0
; RV64XTHEADBS-NEXT: andi a0, a0, 1

14
llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
View File

@ -189,7 +189,7 @@ define void @relax_jal_spill_64() {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: beq t5, t6, .LBB2_1
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: sd s11, 0(sp)
; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: jump .LBB2_4, s11
; CHECK-NEXT: .LBB2_1: # %branch_1
; CHECK-NEXT: #APP
@ -197,7 +197,7 @@ define void @relax_jal_spill_64() {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: j .LBB2_2
; CHECK-NEXT: .LBB2_4: # %branch_2
; CHECK-NEXT: ld s11, 0(sp)
; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: .LBB2_2: # %branch_2
; CHECK-NEXT: #APP
; CHECK-NEXT: # reg use ra
@ -419,7 +419,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-NEXT: addi s0, sp, 2032
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, -2032
; CHECK-NEXT: addi a0, a0, -2032
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: srli a0, sp, 12
; CHECK-NEXT: slli sp, a0, 12
@ -509,7 +509,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: beq t5, t6, .LBB3_1
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: sd s11, 0(sp)
; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: jump .LBB3_4, s11
; CHECK-NEXT: .LBB3_1: # %branch_1
; CHECK-NEXT: #APP
@ -517,7 +517,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: j .LBB3_2
; CHECK-NEXT: .LBB3_4: # %branch_2
; CHECK-NEXT: ld s11, 0(sp)
; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: .LBB3_2: # %branch_2
; CHECK-NEXT: #APP
; CHECK-NEXT: # reg use ra
@ -825,7 +825,7 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
; CHECK-NEXT: bne t5, t6, .LBB4_2
; CHECK-NEXT: j .LBB4_1
; CHECK-NEXT: .LBB4_8: # %dest_1
; CHECK-NEXT: ld s11, 0(sp)
; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: .LBB4_1: # %dest_1
; CHECK-NEXT: #APP
; CHECK-NEXT: # dest 1
@ -962,7 +962,7 @@ define void @relax_jal_spill_64_restore_block_correspondence() {
; CHECK-NEXT: .zero 1048576
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.7: # %space
; CHECK-NEXT: sd s11, 0(sp)
; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: jump .LBB4_8, s11
entry:
%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()

126
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
View File

@ -73,7 +73,7 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a1, a3
@ -129,7 +129,7 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 8
@ -213,7 +213,7 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind {
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: srli a6, a0, 8
; RV64I-NEXT: srliw a7, a0, 24
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: lui a3, 61681
@ -224,8 +224,8 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind {
; RV64I-NEXT: lui a6, 209715
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: slli a7, a7, 32
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a6, a6, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a6, a6, 819
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a5, a5, a7
; RV64I-NEXT: slli a7, a3, 32
@ -293,8 +293,8 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind {
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addiw a1, a1, -241
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a3, a1, 32
; RV64ZBB-NEXT: add a1, a1, a3
; RV64ZBB-NEXT: slli a3, a2, 32
@ -464,20 +464,20 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@ -518,18 +518,18 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind {
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 15
; RV64ZBB-NEXT: srli a2, a0, 44
; RV64ZBB-NEXT: addiw a1, a1, 240
; RV64ZBB-NEXT: addi a1, a1, 240
; RV64ZBB-NEXT: and a1, a2, a1
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: srli a0, a0, 52
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: andi a0, a0, -241
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -598,7 +598,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slliw a0, a0, 24
@ -607,14 +607,14 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
@ -660,21 +660,21 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: srli a2, a0, 36
; RV64ZBB-NEXT: addiw a1, a1, -241
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: and a1, a2, a1
; RV64ZBB-NEXT: lui a2, 986895
; RV64ZBB-NEXT: srli a0, a0, 28
; RV64ZBB-NEXT: addi a2, a2, 240
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -771,7 +771,7 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a6, a0, 8
; RV64I-NEXT: srliw a7, a0, 24
; RV64I-NEXT: lui t0, 61681
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: lui a3, 209715
@ -782,9 +782,9 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a6, 349525
; RV64I-NEXT: and a5, a0, a5
; RV64I-NEXT: slli a7, a7, 32
; RV64I-NEXT: addiw t0, t0, -241
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: addiw a6, a6, 1365
; RV64I-NEXT: addi t0, t0, -241
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: addi a6, a6, 1365
; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a5, a5, a7
; RV64I-NEXT: slli a7, t0, 32
@ -865,9 +865,9 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind {
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addiw a1, a1, -241
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addiw a3, a3, 1365
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32
@ -938,18 +938,18 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@ -988,18 +988,18 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 1
; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -1053,18 +1053,18 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@ -1103,18 +1103,18 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 61681
; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slliw a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -1184,9 +1184,9 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slli a4, a1, 32
; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: slli a4, a2, 32
@ -1255,9 +1255,9 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addiw a1, a1, -241
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addiw a3, a3, 1365
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32
@ -1326,18 +1326,18 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 3
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@ -1376,18 +1376,18 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 1
; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 3
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slli a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 5
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slli a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -1441,18 +1441,18 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slliw a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: slliw a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@ -1491,18 +1491,18 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: srli a1, a0, 4
; RV64ZBB-NEXT: lui a2, 61681
; RV64ZBB-NEXT: addiw a2, a2, -241
; RV64ZBB-NEXT: addi a2, a2, -241
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: slliw a0, a0, 4
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 2
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: lui a2, 349525
; RV64ZBB-NEXT: addiw a2, a2, 1365
; RV64ZBB-NEXT: addi a2, a2, 1365
; RV64ZBB-NEXT: slliw a0, a0, 2
; RV64ZBB-NEXT: or a0, a1, a0
; RV64ZBB-NEXT: srli a1, a0, 1
@ -1572,9 +1572,9 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: addi a1, a1, -241
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: slli a4, a1, 32
; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: slli a4, a2, 32
@ -1643,9 +1643,9 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
; RV64ZBB-NEXT: lui a1, 61681
; RV64ZBB-NEXT: lui a2, 209715
; RV64ZBB-NEXT: lui a3, 349525
; RV64ZBB-NEXT: addiw a1, a1, -241
; RV64ZBB-NEXT: addiw a2, a2, 819
; RV64ZBB-NEXT: addiw a3, a3, 1365
; RV64ZBB-NEXT: addi a1, a1, -241
; RV64ZBB-NEXT: addi a2, a2, 819
; RV64ZBB-NEXT: addi a3, a3, 1365
; RV64ZBB-NEXT: slli a4, a1, 32
; RV64ZBB-NEXT: add a1, a1, a4
; RV64ZBB-NEXT: slli a4, a2, 32

4
llvm/test/CodeGen/RISCV/calling-conv-half.ll
View File

@ -361,7 +361,7 @@ define i32 @caller_half_on_stack() nounwind {
; RV64I-NEXT: li a4, 5
; RV64I-NEXT: li a5, 6
; RV64I-NEXT: li a6, 7
; RV64I-NEXT: addiw t0, a7, -1792
; RV64I-NEXT: addi t0, a7, -1792
; RV64I-NEXT: li a7, 8
; RV64I-NEXT: sd t0, 0(sp)
; RV64I-NEXT: call callee_half_on_stack
@ -510,7 +510,7 @@ define half @callee_half_ret() nounwind {
; RV64IF-LABEL: callee_half_ret:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, 1048564
; RV64IF-NEXT: addiw a0, a0, -1024
; RV64IF-NEXT: addi a0, a0, -1024
; RV64IF-NEXT: ret
;
; RV32-ILP32F-LABEL: callee_half_ret:

2
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
View File

@ -450,7 +450,7 @@ define i256 @callee_large_scalar_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: lui a2, 1018435
; RV64I-NEXT: addiw a2, a2, 747
; RV64I-NEXT: addi a2, a2, 747
; RV64I-NEXT: sd a2, 0(a0)
; RV64I-NEXT: sd a1, 8(a0)
; RV64I-NEXT: sd a1, 16(a0)

6
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
View File

@ -303,21 +303,21 @@ define float @lower_constantpool(float %a) nounwind {
; RV64FINX-SMALL-LABEL: lower_constantpool:
; RV64FINX-SMALL: # %bb.0:
; RV64FINX-SMALL-NEXT: lui a1, 260097
; RV64FINX-SMALL-NEXT: addiw a1, a1, -2048
; RV64FINX-SMALL-NEXT: addi a1, a1, -2048
; RV64FINX-SMALL-NEXT: fadd.s a0, a0, a1
; RV64FINX-SMALL-NEXT: ret
;
; RV64FINX-MEDIUM-LABEL: lower_constantpool:
; RV64FINX-MEDIUM: # %bb.0:
; RV64FINX-MEDIUM-NEXT: lui a1, 260097
; RV64FINX-MEDIUM-NEXT: addiw a1, a1, -2048
; RV64FINX-MEDIUM-NEXT: addi a1, a1, -2048
; RV64FINX-MEDIUM-NEXT: fadd.s a0, a0, a1
; RV64FINX-MEDIUM-NEXT: ret
;
; RV64FINX-LARGE-LABEL: lower_constantpool:
; RV64FINX-LARGE: # %bb.0:
; RV64FINX-LARGE-NEXT: lui a1, 260097
; RV64FINX-LARGE-NEXT: addiw a1, a1, -2048
; RV64FINX-LARGE-NEXT: addi a1, a1, -2048
; RV64FINX-LARGE-NEXT: fadd.s a0, a0, a1
; RV64FINX-LARGE-NEXT: ret
%1 = fadd float %a, 1.000244140625

100
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
View File

@ -163,11 +163,11 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: not a0, a0
; RV64NOZBB-NEXT: lui a2, 5
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: addiw a1, a2, 1365
; RV64NOZBB-NEXT: addi a1, a2, 1365
; RV64NOZBB-NEXT: srli a2, a0, 1
; RV64NOZBB-NEXT: and a1, a2, a1
; RV64NOZBB-NEXT: lui a2, 3
; RV64NOZBB-NEXT: addiw a2, a2, 819
; RV64NOZBB-NEXT: addi a2, a2, 819
; RV64NOZBB-NEXT: sub a0, a0, a1
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
@ -671,11 +671,11 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: not a0, a0
; RV64NOZBB-NEXT: lui a2, 5
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: addiw a1, a2, 1365
; RV64NOZBB-NEXT: addi a1, a2, 1365
; RV64NOZBB-NEXT: srli a2, a0, 1
; RV64NOZBB-NEXT: and a1, a2, a1
; RV64NOZBB-NEXT: lui a2, 3
; RV64NOZBB-NEXT: addiw a2, a2, 819
; RV64NOZBB-NEXT: addi a2, a2, 819
; RV64NOZBB-NEXT: sub a0, a0, a1
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
@ -1131,7 +1131,7 @@ define i16 @test_ctlz_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: srli a1, a1, 49
; RV64NOZBB-NEXT: lui a2, 5
; RV64NOZBB-NEXT: or a0, a0, a1
; RV64NOZBB-NEXT: addiw a1, a2, 1365
; RV64NOZBB-NEXT: addi a1, a2, 1365
; RV64NOZBB-NEXT: slli a2, a0, 48
; RV64NOZBB-NEXT: srli a2, a2, 50
; RV64NOZBB-NEXT: or a0, a0, a2
@ -1145,7 +1145,7 @@ define i16 @test_ctlz_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: srli a2, a0, 1
; RV64NOZBB-NEXT: and a1, a2, a1
; RV64NOZBB-NEXT: lui a2, 3
; RV64NOZBB-NEXT: addiw a2, a2, 819
; RV64NOZBB-NEXT: addi a2, a2, 819
; RV64NOZBB-NEXT: sub a0, a0, a1
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
@ -1243,7 +1243,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -1256,7 +1256,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -1325,7 +1325,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64M-NEXT: srliw a1, a0, 1
; RV64M-NEXT: lui a2, 349525
; RV64M-NEXT: or a0, a0, a1
; RV64M-NEXT: addiw a1, a2, 1365
; RV64M-NEXT: addi a1, a2, 1365
; RV64M-NEXT: srliw a2, a0, 2
; RV64M-NEXT: or a0, a0, a2
; RV64M-NEXT: srliw a2, a0, 4
@ -1338,7 +1338,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64M-NEXT: srli a2, a0, 1
; RV64M-NEXT: and a1, a2, a1
; RV64M-NEXT: lui a2, 209715
; RV64M-NEXT: addiw a2, a2, 819
; RV64M-NEXT: addi a2, a2, 819
; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: and a1, a0, a2
; RV64M-NEXT: srli a0, a0, 2
@ -1468,8 +1468,8 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
@ -1488,7 +1488,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -1592,9 +1592,9 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV64M-NEXT: lui a3, 209715
; RV64M-NEXT: lui a4, 61681
; RV64M-NEXT: or a0, a0, a1
; RV64M-NEXT: addiw a1, a2, 1365
; RV64M-NEXT: addiw a2, a3, 819
; RV64M-NEXT: addiw a3, a4, -241
; RV64M-NEXT: addi a1, a2, 1365
; RV64M-NEXT: addi a2, a3, 819
; RV64M-NEXT: addi a3, a4, -241
; RV64M-NEXT: srli a4, a0, 2
; RV64M-NEXT: or a0, a0, a4
; RV64M-NEXT: slli a4, a1, 32
@ -1619,7 +1619,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV64M-NEXT: srli a0, a0, 2
; RV64M-NEXT: and a0, a0, a2
; RV64M-NEXT: lui a2, 4112
; RV64M-NEXT: addiw a2, a2, 257
; RV64M-NEXT: addi a2, a2, 257
; RV64M-NEXT: add a0, a1, a0
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
@ -1788,7 +1788,7 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: slli a1, a0, 48
; RV64NOZBB-NEXT: lui a2, 5
; RV64NOZBB-NEXT: srli a1, a1, 49
; RV64NOZBB-NEXT: addiw a2, a2, 1365
; RV64NOZBB-NEXT: addi a2, a2, 1365
; RV64NOZBB-NEXT: or a0, a0, a1
; RV64NOZBB-NEXT: slli a1, a0, 48
; RV64NOZBB-NEXT: srli a1, a1, 50
@ -1803,7 +1803,7 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: srli a1, a0, 1
; RV64NOZBB-NEXT: and a1, a1, a2
; RV64NOZBB-NEXT: lui a2, 3
; RV64NOZBB-NEXT: addiw a2, a2, 819
; RV64NOZBB-NEXT: addi a2, a2, 819
; RV64NOZBB-NEXT: sub a0, a0, a1
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
@ -1886,7 +1886,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -1899,7 +1899,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -1957,7 +1957,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: srliw a1, a0, 1
; RV64M-NEXT: lui a2, 349525
; RV64M-NEXT: or a0, a0, a1
; RV64M-NEXT: addiw a1, a2, 1365
; RV64M-NEXT: addi a1, a2, 1365
; RV64M-NEXT: srliw a2, a0, 2
; RV64M-NEXT: or a0, a0, a2
; RV64M-NEXT: srliw a2, a0, 4
@ -1970,7 +1970,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: srli a2, a0, 1
; RV64M-NEXT: and a1, a2, a1
; RV64M-NEXT: lui a2, 209715
; RV64M-NEXT: addiw a2, a2, 819
; RV64M-NEXT: addi a2, a2, 819
; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: and a1, a0, a2
; RV64M-NEXT: srli a0, a0, 2
@ -2088,8 +2088,8 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
@ -2108,7 +2108,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -2200,9 +2200,9 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64M-NEXT: lui a3, 209715
; RV64M-NEXT: lui a4, 61681
; RV64M-NEXT: or a0, a0, a1
; RV64M-NEXT: addiw a1, a2, 1365
; RV64M-NEXT: addiw a2, a3, 819
; RV64M-NEXT: addiw a3, a4, -241
; RV64M-NEXT: addi a1, a2, 1365
; RV64M-NEXT: addi a2, a3, 819
; RV64M-NEXT: addi a3, a4, -241
; RV64M-NEXT: srli a4, a0, 2
; RV64M-NEXT: or a0, a0, a4
; RV64M-NEXT: slli a4, a1, 32
@ -2227,7 +2227,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64M-NEXT: srli a0, a0, 2
; RV64M-NEXT: and a0, a0, a2
; RV64M-NEXT: lui a2, 4112
; RV64M-NEXT: addiw a2, a2, 257
; RV64M-NEXT: addi a2, a2, 257
; RV64M-NEXT: add a0, a1, a0
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
@ -2375,10 +2375,10 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: srli a1, a0, 1
; RV64NOZBB-NEXT: lui a2, 5
; RV64NOZBB-NEXT: addiw a2, a2, 1365
; RV64NOZBB-NEXT: addi a2, a2, 1365
; RV64NOZBB-NEXT: and a1, a1, a2
; RV64NOZBB-NEXT: lui a2, 3
; RV64NOZBB-NEXT: addiw a2, a2, 819
; RV64NOZBB-NEXT: addi a2, a2, 819
; RV64NOZBB-NEXT: sub a0, a0, a1
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
@ -2428,10 +2428,10 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srli a1, a0, 1
; RV64XTHEADBB-NEXT: lui a2, 5
; RV64XTHEADBB-NEXT: addiw a2, a2, 1365
; RV64XTHEADBB-NEXT: addi a2, a2, 1365
; RV64XTHEADBB-NEXT: and a1, a1, a2
; RV64XTHEADBB-NEXT: lui a2, 3
; RV64XTHEADBB-NEXT: addiw a2, a2, 819
; RV64XTHEADBB-NEXT: addi a2, a2, 819
; RV64XTHEADBB-NEXT: sub a0, a0, a1
; RV64XTHEADBB-NEXT: and a1, a0, a2
; RV64XTHEADBB-NEXT: srli a0, a0, 2
@ -2477,10 +2477,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -2526,10 +2526,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64M: # %bb.0:
; RV64M-NEXT: srli a1, a0, 1
; RV64M-NEXT: lui a2, 349525
; RV64M-NEXT: addiw a2, a2, 1365
; RV64M-NEXT: addi a2, a2, 1365
; RV64M-NEXT: and a1, a1, a2
; RV64M-NEXT: lui a2, 209715
; RV64M-NEXT: addiw a2, a2, 819
; RV64M-NEXT: addi a2, a2, 819
; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: and a1, a0, a2
; RV64M-NEXT: srli a0, a0, 2
@ -2585,10 +2585,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: srli a1, a0, 1
; RV64XTHEADBB-NEXT: lui a2, 349525
; RV64XTHEADBB-NEXT: addiw a2, a2, 1365
; RV64XTHEADBB-NEXT: addi a2, a2, 1365
; RV64XTHEADBB-NEXT: and a1, a1, a2
; RV64XTHEADBB-NEXT: lui a2, 209715
; RV64XTHEADBB-NEXT: addiw a2, a2, 819
; RV64XTHEADBB-NEXT: addi a2, a2, 819
; RV64XTHEADBB-NEXT: sub a0, a0, a1
; RV64XTHEADBB-NEXT: and a1, a0, a2
; RV64XTHEADBB-NEXT: srli a0, a0, 2
@ -2656,8 +2656,8 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a3, a1, 32
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a2, 32
@ -2665,7 +2665,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -2728,9 +2728,9 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64M-NEXT: lui a1, 349525
; RV64M-NEXT: lui a2, 209715
; RV64M-NEXT: lui a3, 61681
; RV64M-NEXT: addiw a1, a1, 1365
; RV64M-NEXT: addiw a2, a2, 819
; RV64M-NEXT: addiw a3, a3, -241
; RV64M-NEXT: addi a1, a1, 1365
; RV64M-NEXT: addi a2, a2, 819
; RV64M-NEXT: addi a3, a3, -241
; RV64M-NEXT: slli a4, a1, 32
; RV64M-NEXT: add a1, a1, a4
; RV64M-NEXT: slli a4, a2, 32
@ -2744,7 +2744,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64M-NEXT: srli a0, a0, 2
; RV64M-NEXT: and a0, a0, a2
; RV64M-NEXT: lui a2, 4112
; RV64M-NEXT: addiw a2, a2, 257
; RV64M-NEXT: addi a2, a2, 257
; RV64M-NEXT: add a0, a1, a0
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
@ -2814,8 +2814,8 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: lui a1, 349525
; RV64XTHEADBB-NEXT: lui a2, 209715
; RV64XTHEADBB-NEXT: addiw a1, a1, 1365
; RV64XTHEADBB-NEXT: addiw a2, a2, 819
; RV64XTHEADBB-NEXT: addi a1, a1, 1365
; RV64XTHEADBB-NEXT: addi a2, a2, 819
; RV64XTHEADBB-NEXT: slli a3, a1, 32
; RV64XTHEADBB-NEXT: add a1, a1, a3
; RV64XTHEADBB-NEXT: slli a3, a2, 32
@ -2823,7 +2823,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64XTHEADBB-NEXT: srli a3, a0, 1
; RV64XTHEADBB-NEXT: and a1, a3, a1
; RV64XTHEADBB-NEXT: lui a3, 61681
; RV64XTHEADBB-NEXT: addiw a3, a3, -241
; RV64XTHEADBB-NEXT: addi a3, a3, -241
; RV64XTHEADBB-NEXT: sub a0, a0, a1
; RV64XTHEADBB-NEXT: and a1, a0, a2
; RV64XTHEADBB-NEXT: srli a0, a0, 2

6
llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
View File

@ -732,8 +732,8 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
@ -752,7 +752,7 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2

32
llvm/test/CodeGen/RISCV/div-by-constant.ll
View File

@ -64,7 +64,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: zext.w a1, a0
; RV64IMZB-NEXT: lui a2, 149797
; RV64IMZB-NEXT: addiw a2, a2, -1755
; RV64IMZB-NEXT: addi a2, a2, -1755
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 32
; RV64IMZB-NEXT: subw a0, a0, a1
@ -104,7 +104,7 @@ define i64 @udiv64_constant_no_add(i64 %a) nounwind {
; RV64-LABEL: udiv64_constant_no_add:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 838861
; RV64-NEXT: addiw a1, a1, -819
; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a2, a1, 32
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: mulhu a0, a0, a1
@ -282,7 +282,7 @@ define i32 @sdiv_constant_no_srai(i32 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a1, a1, 1366
; RV64-NEXT: addi a1, a1, 1366
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srli a1, a0, 63
; RV64-NEXT: srli a0, a0, 32
@ -308,7 +308,7 @@ define i32 @sdiv_constant_srai(i32 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: lui a1, 419430
; RV64-NEXT: addiw a1, a1, 1639
; RV64-NEXT: addi a1, a1, 1639
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srli a1, a0, 63
; RV64-NEXT: srai a0, a0, 33
@ -335,7 +335,7 @@ define i32 @sdiv_constant_add_srai(i32 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a1, a0
; RV64-NEXT: lui a2, 599186
; RV64-NEXT: addiw a2, a2, 1171
; RV64-NEXT: addi a2, a2, 1171
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: add a0, a1, a0
@ -364,7 +364,7 @@ define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a1, a0
; RV64-NEXT: lui a2, 449390
; RV64-NEXT: addiw a2, a2, -1171
; RV64-NEXT: addi a2, a2, -1171
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: subw a1, a1, a0
@ -440,7 +440,7 @@ define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {
; RV64-LABEL: sdiv64_constant_add_srai:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 559241
; RV64-NEXT: addiw a1, a1, -1911
; RV64-NEXT: addi a1, a1, -1911
; RV64-NEXT: slli a2, a1, 32
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: mulh a1, a0, a1
@ -468,7 +468,7 @@ define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {
; RV64-LABEL: sdiv64_constant_sub_srai:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a2, a1, 32
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: mulh a1, a0, a1
@ -718,7 +718,7 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 5
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1366
; RV64IM-NEXT: addi a1, a1, 1366
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srli a0, a0, 16
@ -729,7 +729,7 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: lui a1, 5
; RV64IMZB-NEXT: addiw a1, a1, 1366
; RV64IMZB-NEXT: addi a1, a1, 1366
; RV64IMZB-NEXT: mul a0, a0, a1
; RV64IMZB-NEXT: srli a1, a0, 63
; RV64IMZB-NEXT: srli a0, a0, 16
@ -768,7 +768,7 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: addi a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srai a0, a0, 17
@ -779,7 +779,7 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: lui a1, 6
; RV64IMZB-NEXT: addiw a1, a1, 1639
; RV64IMZB-NEXT: addi a1, a1, 1639
; RV64IMZB-NEXT: mul a0, a0, a1
; RV64IMZB-NEXT: srli a1, a0, 63
; RV64IMZB-NEXT: srai a0, a0, 17
@ -824,7 +824,7 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV64IM-NEXT: slli a1, a0, 48
; RV64IM-NEXT: lui a2, 1048569
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: addiw a2, a2, -1911
; RV64IM-NEXT: addi a2, a2, -1911
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 16
; RV64IM-NEXT: add a0, a1, a0
@ -838,7 +838,7 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.h a1, a0
; RV64IMZB-NEXT: lui a2, 1048569
; RV64IMZB-NEXT: addiw a2, a2, -1911
; RV64IMZB-NEXT: addi a2, a2, -1911
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
; RV64IMZB-NEXT: add a0, a1, a0
@ -886,7 +886,7 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IM-NEXT: slli a1, a0, 48
; RV64IM-NEXT: lui a2, 7
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: addiw a2, a2, 1911
; RV64IM-NEXT: addi a2, a2, 1911
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 16
; RV64IM-NEXT: subw a1, a1, a0
@ -900,7 +900,7 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.h a1, a0
; RV64IMZB-NEXT: lui a2, 7
; RV64IMZB-NEXT: addiw a2, a2, 1911
; RV64IMZB-NEXT: addi a2, a2, 1911
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
; RV64IMZB-NEXT: subw a1, a1, a0

8
llvm/test/CodeGen/RISCV/div.ll
View File

@ -211,7 +211,7 @@ define i64 @udiv64_constant(i64 %a) nounwind {
; RV64IM-LABEL: udiv64_constant:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 838861
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: slli a2, a1, 32
; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: mulhu a0, a0, a1
@ -441,7 +441,7 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: call __udivdi3
@ -638,7 +638,7 @@ define i32 @sdiv_constant(i32 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 419430
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: addi a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srai a0, a0, 33
@ -1189,7 +1189,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: addi a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srai a0, a0, 17

2
llvm/test/CodeGen/RISCV/double-convert.ll
View File

@ -1937,7 +1937,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: blez a0, .LBB28_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv a0, a1

22
llvm/test/CodeGen/RISCV/float-convert.ll
View File

@ -126,7 +126,7 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: lui s1, 524288
; RV64I-NEXT: .LBB1_2: # %start
; RV64I-NEXT: lui a1, 323584
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB1_4
@ -311,7 +311,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a1, 325632
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB4_2
@ -788,7 +788,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: slli s1, s3, 63
; RV64I-NEXT: .LBB12_2: # %start
; RV64I-NEXT: lui a1, 389120
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB12_4
@ -976,7 +976,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 391168
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: neg s1, a0
@ -1462,7 +1462,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IZFINX-NEXT: fmax.s a0, a0, a2
; RV64IZFINX-NEXT: lui a2, 290816
; RV64IZFINX-NEXT: neg a1, a1
; RV64IZFINX-NEXT: addiw a2, a2, -512
; RV64IZFINX-NEXT: addi a2, a2, -512
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZFINX-NEXT: and a0, a1, a0
@ -1529,7 +1529,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB24_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB24_4
@ -1633,7 +1633,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: fmax.s a0, a0, zero
; RV64IZFINX-NEXT: lui a1, 292864
; RV64IZFINX-NEXT: addiw a1, a1, -256
; RV64IZFINX-NEXT: addi a1, a1, -256
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZFINX-NEXT: ret
@ -1690,11 +1690,11 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addiw a1, a0, -256
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: blez a0, .LBB26_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv a0, a1
@ -2132,7 +2132,7 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind {
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a1, 325632
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB31_2
@ -2240,7 +2240,7 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV64I-NEXT: lui s1, 524288
; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: lui a1, 323584
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB32_4

22
llvm/test/CodeGen/RISCV/float-imm.ll
View File

@ -16,19 +16,12 @@ define float @float_imm() nounwind {
; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: ret
;
; RV32ZFINX-LABEL: float_imm:
; RV32ZFINX: # %bb.0:
; RV32ZFINX-NEXT: lui a0, 263313
; RV32ZFINX-NEXT: addi a0, a0, -37
; RV32ZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
; RV32ZFINX-NEXT: ret
;
; RV64ZFINX-LABEL: float_imm:
; RV64ZFINX: # %bb.0:
; RV64ZFINX-NEXT: lui a0, 263313
; RV64ZFINX-NEXT: addiw a0, a0, -37
; RV64ZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
; RV64ZFINX-NEXT: ret
; CHECKZFINX-LABEL: float_imm:
; CHECKZFINX: # %bb.0:
; CHECKZFINX-NEXT: lui a0, 263313
; CHECKZFINX-NEXT: addi a0, a0, -37
; CHECKZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
; CHECKZFINX-NEXT: ret
ret float 3.14159274101257324218750
}
@ -75,3 +68,6 @@ define float @float_negative_zero(ptr %pf) nounwind {
; CHECKZFINX-NEXT: ret
ret float -0.0
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32ZFINX: {{.*}}
; RV64ZFINX: {{.*}}

6
llvm/test/CodeGen/RISCV/float-intrinsics.ll
View File

@ -1655,7 +1655,7 @@ define i1 @fpclass(float %x) {
; RV64I-NEXT: lui a3, 522240
; RV64I-NEXT: lui a4, 1046528
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: slti a1, a1, 0
; RV64I-NEXT: addi a5, a0, -1
; RV64I-NEXT: sltu a2, a5, a2
@ -1764,7 +1764,7 @@ define i1 @isqnan_fpclass(float %x) {
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: lui a1, 523264
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; qnan
@ -2153,7 +2153,7 @@ define i1 @isnotfinite_fpclass(float %x) {
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: lui a1, 522240
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"

6
llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
View File

@ -1263,7 +1263,7 @@ define i1 @pr134525() nounwind {
; RV64I-NEXT: lui a0, %hi(ki_end+2145386496)
; RV64I-NEXT: addi a0, a0, %lo(ki_end+2145386496)
; RV64I-NEXT: lui a1, 32
; RV64I-NEXT: addiw a1, a1, 1
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
;
@ -1275,7 +1275,7 @@ define i1 @pr134525() nounwind {
; RV64I-MEDIUM-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi15)
; RV64I-MEDIUM-NEXT: add a0, a0, a1
; RV64I-MEDIUM-NEXT: lui a1, 32
; RV64I-MEDIUM-NEXT: addiw a1, a1, 1
; RV64I-MEDIUM-NEXT: addi a1, a1, 1
; RV64I-MEDIUM-NEXT: sltu a0, a0, a1
; RV64I-MEDIUM-NEXT: ret
;
@ -1287,7 +1287,7 @@ define i1 @pr134525() nounwind {
; RV64I-LARGE-NEXT: lui a1, 523776
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: lui a1, 32
; RV64I-LARGE-NEXT: addiw a1, a1, 1
; RV64I-LARGE-NEXT: addi a1, a1, 1
; RV64I-LARGE-NEXT: sltu a0, a0, a1
; RV64I-LARGE-NEXT: ret
entry:

5
llvm/test/CodeGen/RISCV/fold-mem-offset.ll
View File

@ -575,12 +575,11 @@ define signext i32 @test_large_offset(ptr %p, iXLen %x, iXLen %y) {
; RV64I-NEXT: lui a3, 2
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: slli a2, a2, 2
; RV64I-NEXT: addiw a3, a3, -1392
; RV64I-NEXT: add a0, a0, a3
; RV64I-NEXT: add a1, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: lw a1, 0(a1)
; RV64I-NEXT: lw a0, 40(a0)
; RV64I-NEXT: lw a1, -1392(a1)
; RV64I-NEXT: lw a0, -1352(a0)
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;

48
llvm/test/CodeGen/RISCV/fpclamptosat.ll
View File

@ -585,7 +585,7 @@ define i16 @stest_f64i16(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: lui a1, 8
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: blt a0, a1, .LBB9_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -624,7 +624,7 @@ define i16 @stest_f64i16(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 8
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: bge a0, a1, .LBB9_3
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: lui a1, 1048568
@ -676,7 +676,7 @@ define i16 @utest_f64i16(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixunsdfsi
; RV64IF-NEXT: lui a1, 16
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: bltu a0, a1, .LBB10_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -702,7 +702,7 @@ define i16 @utest_f64i16(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 16
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: bltu a0, a1, .LBB10_2
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: mv a0, a1
@ -747,7 +747,7 @@ define i16 @ustest_f64i16(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: lui a1, 16
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: blt a0, a1, .LBB11_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -779,7 +779,7 @@ define i16 @ustest_f64i16(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 16
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: blt a0, a1, .LBB11_2
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: mv a0, a1
@ -822,7 +822,7 @@ define i16 @stest_f32i16(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.w.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bge a0, a1, .LBB12_3
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: lui a1, 1048568
@ -862,7 +862,7 @@ define i16 @utest_f32i16(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bltu a0, a1, .LBB13_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -895,7 +895,7 @@ define i16 @ustest_f32i16(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.w.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB14_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -949,7 +949,7 @@ define i16 @stest_f16i16(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB15_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -1004,7 +1004,7 @@ define i16 @utesth_f16i16(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bltu a0, a1, .LBB16_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -1055,7 +1055,7 @@ define i16 @ustest_f16i16(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB17_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -2536,7 +2536,7 @@ define i16 @stest_f64i16_mm(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: lui a1, 8
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: blt a0, a1, .LBB36_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -2575,7 +2575,7 @@ define i16 @stest_f64i16_mm(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 8
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: bge a0, a1, .LBB36_3
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: lui a1, 1048568
@ -2625,7 +2625,7 @@ define i16 @utest_f64i16_mm(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixunsdfsi
; RV64IF-NEXT: lui a1, 16
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: bltu a0, a1, .LBB37_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -2651,7 +2651,7 @@ define i16 @utest_f64i16_mm(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 16
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: bltu a0, a1, .LBB37_2
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: mv a0, a1
@ -2695,7 +2695,7 @@ define i16 @ustest_f64i16_mm(double %x) {
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: call __fixdfsi
; RV64IF-NEXT: lui a1, 16
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: blt a0, a1, .LBB38_2
; RV64IF-NEXT: # %bb.1: # %entry
; RV64IF-NEXT: mv a0, a1
@ -2727,7 +2727,7 @@ define i16 @ustest_f64i16_mm(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 16
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: blt a0, a1, .LBB38_2
; RV64IFD-NEXT: # %bb.1: # %entry
; RV64IFD-NEXT: mv a0, a1
@ -2768,7 +2768,7 @@ define i16 @stest_f32i16_mm(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.w.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bge a0, a1, .LBB39_3
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: lui a1, 1048568
@ -2806,7 +2806,7 @@ define i16 @utest_f32i16_mm(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bltu a0, a1, .LBB40_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -2838,7 +2838,7 @@ define i16 @ustest_f32i16_mm(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fcvt.w.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB41_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -2890,7 +2890,7 @@ define i16 @stest_f16i16_mm(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB42_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -2943,7 +2943,7 @@ define i16 @utesth_f16i16_mm(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: bltu a0, a1, .LBB43_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1
@ -2993,7 +2993,7 @@ define i16 @ustest_f16i16_mm(half %x) {
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: fcvt.l.s a0, fa0, rtz
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -1
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: blt a0, a1, .LBB44_2
; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1

6
llvm/test/CodeGen/RISCV/fpenv.ll
View File

@ -18,7 +18,7 @@ define i32 @func_01() {
; RV64IF-NEXT: frrm a0
; RV64IF-NEXT: lui a1, 66
; RV64IF-NEXT: slli a0, a0, 2
; RV64IF-NEXT: addiw a1, a1, 769
; RV64IF-NEXT: addi a1, a1, 769
; RV64IF-NEXT: srl a0, a1, a0
; RV64IF-NEXT: andi a0, a0, 7
; RV64IF-NEXT: ret
@ -77,7 +77,7 @@ define i1 @test_get_rounding_sideeffect() #0 {
; RV64IF-NEXT: frrm a0
; RV64IF-NEXT: lui a1, 66
; RV64IF-NEXT: slli a0, a0, 2
; RV64IF-NEXT: addiw s0, a1, 769
; RV64IF-NEXT: addi s0, a1, 769
; RV64IF-NEXT: srl a0, s0, a0
; RV64IF-NEXT: andi a0, a0, 7
; RV64IF-NEXT: beqz a0, .LBB1_2
@ -133,7 +133,7 @@ define void @func_02(i32 %rm) {
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: lui a1, 66
; RV64IF-NEXT: srli a0, a0, 30
; RV64IF-NEXT: addiw a1, a1, 769
; RV64IF-NEXT: addi a1, a1, 769
; RV64IF-NEXT: srl a0, a1, a0
; RV64IF-NEXT: andi a0, a0, 7
; RV64IF-NEXT: fsrm a0

44
llvm/test/CodeGen/RISCV/half-arith.ll
View File

@ -71,7 +71,7 @@ define half @fadd_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -153,7 +153,7 @@ define half @fsub_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -235,7 +235,7 @@ define half @fmul_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -317,7 +317,7 @@ define half @fdiv_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -546,7 +546,7 @@ define i32 @fneg_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: addi s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv a1, a0
@ -667,7 +667,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind {
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: addi s3, a0, -1
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -831,7 +831,7 @@ define half @fabs_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -972,7 +972,7 @@ define half @fmin_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -1056,7 +1056,7 @@ define half @fmax_h(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -1149,7 +1149,7 @@ define half @fmadd_h(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -1261,7 +1261,7 @@ define half @fmsub_h(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: addi s3, a0, -1
; RV64I-NEXT: and a0, a2, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -1416,7 +1416,7 @@ define half @fnmadd_h(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui s3, 16
; RV64I-NEXT: addiw s3, s3, -1
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -1596,7 +1596,7 @@ define half @fnmadd_h_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui s3, 16
; RV64I-NEXT: addiw s3, s3, -1
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: and a0, a1, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -1761,7 +1761,7 @@ define half @fnmadd_h_3(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -1882,7 +1882,7 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -2003,7 +2003,7 @@ define half @fnmsub_h(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -2140,7 +2140,7 @@ define half @fnmsub_h_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: addi s3, a0, -1
; RV64I-NEXT: and a0, a1, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -2269,7 +2269,7 @@ define half @fmadd_h_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -2393,7 +2393,7 @@ define half @fmsub_h_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: addi s3, a0, -1
; RV64I-NEXT: and a0, a2, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -2552,7 +2552,7 @@ define half @fnmadd_h_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui s3, 16
; RV64I-NEXT: addiw s3, s3, -1
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -2737,7 +2737,7 @@ define half @fnmsub_h_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui s3, 16
; RV64I-NEXT: addiw s3, s3, -1
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: li a1, 0
@ -2871,7 +2871,7 @@ define half @fsgnjx_f16(half %x, half %y) nounwind {
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a0, 12
; RV64I-NEXT: addiw a0, a0, -1024
; RV64I-NEXT: addi a0, a0, -1024
; RV64I-NEXT: and a0, s1, a0
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv a1, s0

58
llvm/test/CodeGen/RISCV/half-convert.ll
View File

@ -272,7 +272,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZHINX-NEXT: lui a2, 290816
; RV64IZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZHINX-NEXT: feq.s a0, a0, a0
; RV64IZHINX-NEXT: addiw a2, a2, -512
; RV64IZHINX-NEXT: addi a2, a2, -512
; RV64IZHINX-NEXT: neg a0, a0
; RV64IZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZHINX-NEXT: fcvt.l.s a1, a1, rtz
@ -300,7 +300,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: lui a2, 290816
; RV64IZDINXZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZDINXZHINX-NEXT: feq.s a0, a0, a0
; RV64IZDINXZHINX-NEXT: addiw a2, a2, -512
; RV64IZDINXZHINX-NEXT: addi a2, a2, -512
; RV64IZDINXZHINX-NEXT: neg a0, a0
; RV64IZDINXZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a1, a1, rtz
@ -372,13 +372,13 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB1_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB1_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: lui s1, 8
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB1_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
@ -522,7 +522,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: lui a2, 290816
; CHECK64-IZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: addi a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
@ -550,7 +550,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 290816
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: addi a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
@ -768,7 +768,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 292864
; RV64IZHINX-NEXT: fmax.s a0, a0, zero
; RV64IZHINX-NEXT: addiw a1, a1, -256
; RV64IZHINX-NEXT: addi a1, a1, -256
; RV64IZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZHINX-NEXT: ret
@ -788,7 +788,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: lui a1, 292864
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, zero
; RV64IZDINXZHINX-NEXT: addiw a1, a1, -256
; RV64IZDINXZHINX-NEXT: addi a1, a1, -256
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZDINXZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
@ -840,7 +840,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui s0, 16
; RV64I-NEXT: addiw s0, s0, -1
; RV64I-NEXT: addi s0, s0, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s3, a0
@ -851,7 +851,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addiw a1, a0, -256
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: bgtz a0, .LBB3_2
@ -968,7 +968,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a1, 292864
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, zero
; CHECK64-IZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: addi a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
@ -988,7 +988,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 292864
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: addi a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
@ -1244,7 +1244,7 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64I-NEXT: lui s1, 524288
; RV64I-NEXT: .LBB5_2: # %start
; RV64I-NEXT: lui a1, 323584
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB5_4
@ -1819,7 +1819,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a1, 325632
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB8_2
@ -2411,7 +2411,7 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64I-NEXT: slli s1, s3, 63
; RV64I-NEXT: .LBB10_2: # %start
; RV64I-NEXT: lui a1, 389120
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB10_4
@ -3076,7 +3076,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 391168
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: neg s1, a0
@ -6374,7 +6374,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZHINX-NEXT: lui a2, 290816
; RV64IZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZHINX-NEXT: feq.s a0, a0, a0
; RV64IZHINX-NEXT: addiw a2, a2, -512
; RV64IZHINX-NEXT: addi a2, a2, -512
; RV64IZHINX-NEXT: neg a0, a0
; RV64IZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZHINX-NEXT: fcvt.l.s a1, a1, rtz
@ -6402,7 +6402,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: lui a2, 290816
; RV64IZDINXZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZDINXZHINX-NEXT: feq.s a0, a0, a0
; RV64IZDINXZHINX-NEXT: addiw a2, a2, -512
; RV64IZDINXZHINX-NEXT: addi a2, a2, -512
; RV64IZDINXZHINX-NEXT: neg a0, a0
; RV64IZDINXZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a1, a1, rtz
@ -6476,7 +6476,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB32_4
@ -6628,7 +6628,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: lui a2, 290816
; CHECK64-IZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: addi a2, a2, -512
; CHECK64-IZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
@ -6656,7 +6656,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, 290816
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: addi a2, a2, -512
; CHECK64-IZDINXZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
@ -6873,7 +6873,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 292864
; RV64IZHINX-NEXT: fmax.s a0, a0, zero
; RV64IZHINX-NEXT: addiw a1, a1, -256
; RV64IZHINX-NEXT: addi a1, a1, -256
; RV64IZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZHINX-NEXT: ret
@ -6893,7 +6893,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: lui a1, 292864
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, zero
; RV64IZDINXZHINX-NEXT: addiw a1, a1, -256
; RV64IZDINXZHINX-NEXT: addi a1, a1, -256
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a1
; RV64IZDINXZHINX-NEXT: fcvt.lu.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
@ -6948,7 +6948,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui s3, 16
; RV64I-NEXT: addiw s3, s3, -1
; RV64I-NEXT: addi s3, s3, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -6959,7 +6959,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addiw a1, a0, -256
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB34_2
@ -7079,7 +7079,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a1, 292864
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, zero
; CHECK64-IZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: addi a1, a1, -256
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
@ -7099,7 +7099,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 292864
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, zero
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: addi a1, a1, -256
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
@ -8175,7 +8175,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a1, 325632
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB39_2
@ -8444,7 +8444,7 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64I-NEXT: lui s1, 524288
; RV64I-NEXT: .LBB40_2: # %start
; RV64I-NEXT: lui a1, 323584
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB40_4

24
llvm/test/CodeGen/RISCV/half-imm.ll
View File

@ -38,7 +38,7 @@ define half @half_imm() nounwind {
; RV64IZHINX-LABEL: half_imm:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: lui a0, 4
; RV64IZHINX-NEXT: addiw a0, a0, 512
; RV64IZHINX-NEXT: addi a0, a0, 512
; RV64IZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV64IZHINX-NEXT: ret
;
@ -48,19 +48,12 @@ define half @half_imm() nounwind {
; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECKIZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: half_imm:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: lui a0, 4
; RV32IZHINXMIN-NEXT: addi a0, a0, 512
; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: half_imm:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: lui a0, 4
; RV64IZHINXMIN-NEXT: addiw a0, a0, 512
; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; RV64IZHINXMIN-NEXT: ret
; CHECKIZHINXMIN-LABEL: half_imm:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: lui a0, 4
; CHECKIZHINXMIN-NEXT: addi a0, a0, 512
; CHECKIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
; CHECKIZHINXMIN-NEXT: ret
ret half 3.0
}
@ -163,3 +156,6 @@ define half @half_negative_zero(ptr %pf) nounwind {
; CHECKIZHINXMIN-NEXT: ret
ret half -0.0
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32IZHINXMIN: {{.*}}
; RV64IZHINXMIN: {{.*}}

18
llvm/test/CodeGen/RISCV/half-intrinsics.ll
View File

@ -649,7 +649,7 @@ define half @sincos_f16(half %a) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s0, a0
@ -905,7 +905,7 @@ define half @pow_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -1748,7 +1748,7 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -1853,7 +1853,7 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: addi s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
@ -2015,7 +2015,7 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -2099,7 +2099,7 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -3143,7 +3143,7 @@ define half @maximumnum_half(half %x, half %y) {
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -3247,7 +3247,7 @@ define half @minimumnum_half(half %x, half %y) {
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0
@ -3990,7 +3990,7 @@ define half @atan2_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0

22
llvm/test/CodeGen/RISCV/i64-icmp.ll
View File

@ -28,7 +28,7 @@ define i64 @icmp_eq_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2047
; RV64I-NEXT: addi a1, a1, -2047
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
@ -106,7 +106,7 @@ define i64 @icmp_ne_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2047
; RV64I-NEXT: addi a1, a1, -2047
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
@ -226,7 +226,7 @@ define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: addi a1, a1, 2046
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 18446744073709549566 signed extend is -2050
@ -294,7 +294,7 @@ define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: addi a1, a1, 2046
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
; 18446744073709549567 signed extend is -2049
@ -359,7 +359,7 @@ define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 18446744073709549567 signed extend is -2049
@ -425,7 +425,7 @@ define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
; 18446744073709549566 signed extend is -2050
@ -491,7 +491,7 @@ define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: addi a1, a1, 2046
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ret
%1 = icmp sgt i64 %a, -2050
@ -621,7 +621,7 @@ define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_neg_2049:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp slt i64 %a, -2049
@ -686,7 +686,7 @@ define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_neg_2050:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp sle i64 %a, -2050
@ -712,7 +712,7 @@ define i64 @icmp_eq_zext_inreg_large_constant(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: lui a1, 563901
; RV64I-NEXT: addiw a1, a1, -529
; RV64I-NEXT: addi a1, a1, -529
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
@ -753,7 +753,7 @@ define i64 @icmp_ne_zext_inreg_umin(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_zext_inreg_umin:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 30141
; RV64I-NEXT: addiw a1, a1, -747
; RV64I-NEXT: addi a1, a1, -747
; RV64I-NEXT: bltu a0, a1, .LBB67_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1

348
llvm/test/CodeGen/RISCV/imm.ll
View File

File diff suppressed because it is too large Load Diff

18
llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
View File

@ -273,7 +273,7 @@ define void @constraint_m_with_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI5_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)
@ -419,7 +419,7 @@ define void @constraint_m_with_extern_weak_global_3() nounwind {
; RV64I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(ewg)
; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0)
; RV64I-MEDIUM-NEXT: lui a1, 2
; RV64I-MEDIUM-NEXT: addiw a1, a1, -192
; RV64I-MEDIUM-NEXT: addi a1, a1, -192
; RV64I-MEDIUM-NEXT: add a0, a0, a1
; RV64I-MEDIUM-NEXT: #APP
; RV64I-MEDIUM-NEXT: sw zero, 0(a0)
@ -432,7 +432,7 @@ define void @constraint_m_with_extern_weak_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI8_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)
@ -1435,7 +1435,7 @@ define void @constraint_o_with_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI21_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi15)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)
@ -1581,7 +1581,7 @@ define void @constraint_o_with_extern_weak_global_3() nounwind {
; RV64I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(ewg)
; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi18)(a0)
; RV64I-MEDIUM-NEXT: lui a1, 2
; RV64I-MEDIUM-NEXT: addiw a1, a1, -192
; RV64I-MEDIUM-NEXT: addi a1, a1, -192
; RV64I-MEDIUM-NEXT: add a0, a0, a1
; RV64I-MEDIUM-NEXT: #APP
; RV64I-MEDIUM-NEXT: sw zero, 0(a0)
@ -1594,7 +1594,7 @@ define void @constraint_o_with_extern_weak_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI24_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi18)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)
@ -2500,7 +2500,7 @@ define void @constraint_A_with_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI35_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi27)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)
@ -2655,7 +2655,7 @@ define void @constraint_A_with_extern_weak_global_3() nounwind {
; RV64I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(ewg)
; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi30)(a0)
; RV64I-MEDIUM-NEXT: lui a1, 2
; RV64I-MEDIUM-NEXT: addiw a1, a1, -192
; RV64I-MEDIUM-NEXT: addi a1, a1, -192
; RV64I-MEDIUM-NEXT: add a0, a0, a1
; RV64I-MEDIUM-NEXT: #APP
; RV64I-MEDIUM-NEXT: sw zero, 0(a0)
@ -2668,7 +2668,7 @@ define void @constraint_A_with_extern_weak_global_3() nounwind {
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI38_0)
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi30)(a0)
; RV64I-LARGE-NEXT: lui a1, 2
; RV64I-LARGE-NEXT: addiw a1, a1, -192
; RV64I-LARGE-NEXT: addi a1, a1, -192
; RV64I-LARGE-NEXT: add a0, a0, a1
; RV64I-LARGE-NEXT: #APP
; RV64I-LARGE-NEXT: sw zero, 0(a0)

2
llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
View File

@ -766,7 +766,7 @@ define i1 @add_ugecmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sltu a0, a0, a1

6
llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
View File

@ -26,16 +26,16 @@ define void @use_frame_base_reg() {
; RV64I-LABEL: use_frame_base_reg:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: addiw a0, a0, 1712
; RV64I-NEXT: addi a0, a0, 1712
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 100016
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: addiw a0, a0, 1704
; RV64I-NEXT: addi a0, a0, 1704
; RV64I-NEXT: add a0, sp, a0
; RV64I-NEXT: lbu zero, 4(a0)
; RV64I-NEXT: lbu zero, 0(a0)
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: addiw a0, a0, 1712
; RV64I-NEXT: addi a0, a0, 1712
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret

2
llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
View File

@ -57,7 +57,7 @@ define void @test(i32 signext %i) nounwind {
; RV64-NEXT: # %bb.1: # %bb.preheader
; RV64-NEXT: lui a2, %hi(flags2)
; RV64-NEXT: addi a2, a2, %lo(flags2)
; RV64-NEXT: addiw a3, a3, 1
; RV64-NEXT: addi a3, a3, 1
; RV64-NEXT: .LBB0_2: # %bb
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: slli a4, a1, 32

14
llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
View File

@ -77,19 +77,19 @@ define i32 @test_matint() {
; FUSION-LABEL: test_matint:
; FUSION: # %bb.0:
; FUSION-NEXT: lui a0, 1
; FUSION-NEXT: addiw a0, a0, -2048
; FUSION-NEXT: addi a0, a0, -2048
; FUSION-NEXT: ret
;
; FUSION-POSTRA-LABEL: test_matint:
; FUSION-POSTRA: # %bb.0:
; FUSION-POSTRA-NEXT: lui a0, 1
; FUSION-POSTRA-NEXT: addiw a0, a0, -2048
; FUSION-POSTRA-NEXT: addi a0, a0, -2048
; FUSION-POSTRA-NEXT: ret
;
; FUSION-GENERIC-LABEL: test_matint:
; FUSION-GENERIC: # %bb.0:
; FUSION-GENERIC-NEXT: lui a0, 1
; FUSION-GENERIC-NEXT: addiw a0, a0, -2048
; FUSION-GENERIC-NEXT: addi a0, a0, -2048
; FUSION-GENERIC-NEXT: ret
ret i32 2048
}
@ -99,27 +99,27 @@ define void @test_regalloc_hint(i32 noundef signext %0, i32 noundef signext %1)
; NOFUSION: # %bb.0:
; NOFUSION-NEXT: mv a0, a1
; NOFUSION-NEXT: lui a1, 3014
; NOFUSION-NEXT: addiw a1, a1, 334
; NOFUSION-NEXT: addi a1, a1, 334
; NOFUSION-NEXT: tail bar
;
; FUSION-LABEL: test_regalloc_hint:
; FUSION: # %bb.0:
; FUSION-NEXT: mv a0, a1
; FUSION-NEXT: lui a1, 3014
; FUSION-NEXT: addiw a1, a1, 334
; FUSION-NEXT: addi a1, a1, 334
; FUSION-NEXT: tail bar
;
; FUSION-POSTRA-LABEL: test_regalloc_hint:
; FUSION-POSTRA: # %bb.0:
; FUSION-POSTRA-NEXT: mv a0, a1
; FUSION-POSTRA-NEXT: lui a1, 3014
; FUSION-POSTRA-NEXT: addiw a1, a1, 334
; FUSION-POSTRA-NEXT: addi a1, a1, 334
; FUSION-POSTRA-NEXT: tail bar
;
; FUSION-GENERIC-LABEL: test_regalloc_hint:
; FUSION-GENERIC: # %bb.0:
; FUSION-GENERIC-NEXT: lui a2, 3014
; FUSION-GENERIC-NEXT: addiw a2, a2, 334
; FUSION-GENERIC-NEXT: addi a2, a2, 334
; FUSION-GENERIC-NEXT: mv a0, a1
; FUSION-GENERIC-NEXT: mv a1, a2
; FUSION-GENERIC-NEXT: tail bar

16
llvm/test/CodeGen/RISCV/memset-inline.ll
View File

@ -138,7 +138,7 @@ define void @memset_8(ptr %a, i8 %value) nounwind {
; RV64-FAST: # %bb.0:
; RV64-FAST-NEXT: zext.b a1, a1
; RV64-FAST-NEXT: lui a2, 4112
; RV64-FAST-NEXT: addiw a2, a2, 257
; RV64-FAST-NEXT: addi a2, a2, 257
; RV64-FAST-NEXT: slli a3, a2, 32
; RV64-FAST-NEXT: add a2, a2, a3
; RV64-FAST-NEXT: mul a1, a1, a2
@ -205,7 +205,7 @@ define void @memset_16(ptr %a, i8 %value) nounwind {
; RV64-FAST: # %bb.0:
; RV64-FAST-NEXT: zext.b a1, a1
; RV64-FAST-NEXT: lui a2, 4112
; RV64-FAST-NEXT: addiw a2, a2, 257
; RV64-FAST-NEXT: addi a2, a2, 257
; RV64-FAST-NEXT: slli a3, a2, 32
; RV64-FAST-NEXT: add a2, a2, a3
; RV64-FAST-NEXT: mul a1, a1, a2
@ -309,7 +309,7 @@ define void @memset_32(ptr %a, i8 %value) nounwind {
; RV64-FAST: # %bb.0:
; RV64-FAST-NEXT: zext.b a1, a1
; RV64-FAST-NEXT: lui a2, 4112
; RV64-FAST-NEXT: addiw a2, a2, 257
; RV64-FAST-NEXT: addi a2, a2, 257
; RV64-FAST-NEXT: slli a3, a2, 32
; RV64-FAST-NEXT: add a2, a2, a3
; RV64-FAST-NEXT: mul a1, a1, a2
@ -487,7 +487,7 @@ define void @memset_64(ptr %a, i8 %value) nounwind {
; RV64-FAST: # %bb.0:
; RV64-FAST-NEXT: zext.b a1, a1
; RV64-FAST-NEXT: lui a2, 4112
; RV64-FAST-NEXT: addiw a2, a2, 257
; RV64-FAST-NEXT: addi a2, a2, 257
; RV64-FAST-NEXT: slli a3, a2, 32
; RV64-FAST-NEXT: add a2, a2, a3
; RV64-FAST-NEXT: mul a1, a1, a2
@ -564,7 +564,7 @@ define void @aligned_memset_8(ptr align 8 %a, i8 %value) nounwind {
; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: zext.b a1, a1
; RV64-BOTH-NEXT: lui a2, 4112
; RV64-BOTH-NEXT: addiw a2, a2, 257
; RV64-BOTH-NEXT: addi a2, a2, 257
; RV64-BOTH-NEXT: slli a3, a2, 32
; RV64-BOTH-NEXT: add a2, a2, a3
; RV64-BOTH-NEXT: mul a1, a1, a2
@ -591,7 +591,7 @@ define void @aligned_memset_16(ptr align 16 %a, i8 %value) nounwind {
; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: zext.b a1, a1
; RV64-BOTH-NEXT: lui a2, 4112
; RV64-BOTH-NEXT: addiw a2, a2, 257
; RV64-BOTH-NEXT: addi a2, a2, 257
; RV64-BOTH-NEXT: slli a3, a2, 32
; RV64-BOTH-NEXT: add a2, a2, a3
; RV64-BOTH-NEXT: mul a1, a1, a2
@ -623,7 +623,7 @@ define void @aligned_memset_32(ptr align 32 %a, i8 %value) nounwind {
; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: zext.b a1, a1
; RV64-BOTH-NEXT: lui a2, 4112
; RV64-BOTH-NEXT: addiw a2, a2, 257
; RV64-BOTH-NEXT: addi a2, a2, 257
; RV64-BOTH-NEXT: slli a3, a2, 32
; RV64-BOTH-NEXT: add a2, a2, a3
; RV64-BOTH-NEXT: mul a1, a1, a2
@ -665,7 +665,7 @@ define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind {
; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: zext.b a1, a1
; RV64-BOTH-NEXT: lui a2, 4112
; RV64-BOTH-NEXT: addiw a2, a2, 257
; RV64-BOTH-NEXT: addi a2, a2, 257
; RV64-BOTH-NEXT: slli a3, a2, 32
; RV64-BOTH-NEXT: add a2, a2, a3
; RV64-BOTH-NEXT: mul a1, a1, a2

4
llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
View File

@ -246,7 +246,7 @@ define signext i32 @test14(i32 signext %x) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: slliw a0, a0, 10
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -1027
; RV64-NEXT: addi a1, a1, -1027
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
%or = shl i32 %x, 10
@ -269,7 +269,7 @@ define signext i32 @test15(i32 signext %x) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: slliw a0, a0, 10
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, -515
; RV64-NEXT: addi a1, a1, -515
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: ret
%xor = shl i32 %x, 10

98
llvm/test/CodeGen/RISCV/opt-w-instrs.mir
View File

@ -169,3 +169,101 @@ body: |
PseudoRET implicit $x10
...
---
name: lui_addi_1
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: lui_addi_1
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 11
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], -1756
; CHECK-NEXT: BEQ killed [[ADDIW]], [[ADDI]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW $x0, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[ADDI]], %bb.0, [[LW]], %bb.1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprtc = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY1]]
; CHECK-NEXT: $x11 = COPY [[PHI]]
; CHECK-NEXT: PseudoTAILIndirect [[COPY1]], csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
bb.0:
liveins: $x10
%2:gpr = COPY $x10
%4:gpr = ADDIW %2, 0
%5:gpr = LUI 11
%3:gpr = ADDI killed %5, -1756
BEQ killed %4, %3, %bb.2
PseudoBR %bb.1
bb.1:
%0:gpr = LW $x0, 0
bb.2:
%1:gpr = PHI %3, %bb.0, %0, %bb.1
%6:gpr = ADDIW %1, 0
%7:gprtc = COPY $x0
$x10 = COPY %7
$x11 = COPY %6
PseudoTAILIndirect %7, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
...
---
# The sext.w was erroneously removed in an earlier broken version of the patch
# for RISCVOptWInstrs that added lui/addi handling.
name: lui_addi_2
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: lui_addi_2
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524289
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -2048
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`)
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[LWU]], [[ADDI]]
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[AND]], 0
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: %call_target_dummy:gprjalr = COPY $x0
; CHECK-NEXT: PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[LWU]]
; CHECK-NEXT: PseudoRET implicit $x10
bb.0.entry:
%13:gpr = LUI 524289
%14:gpr = ADDI %13, -2048
bb.1:
%1:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`)
%15:gpr = AND %1, %14
%16:gpr = ADDIW killed %15, 0
$x10 = COPY %16
PseudoRET implicit $x10
bb.2:
ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
$x10 = COPY %16
%call_target_dummy:gprjalr = COPY $x0
PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
$x10 = COPY %1
PseudoRET implicit $x10
...

10
llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
View File

@ -28,18 +28,18 @@
; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 2032
; CHECK-NEXT: sd a0, 0(sp)
; CHECK-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, -2032
; CHECK-NEXT: addi a0, a0, -2032
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: srli a0, sp, 12
; CHECK-NEXT: slli sp, a0, 12
; CHECK-NEXT: ld a0, 0(sp)
; CHECK-NEXT: sd a1, 0(sp)
; CHECK-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: lui a1, 1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: sd a0, -8(a1)
; CHECK-NEXT: ld a1, 0(sp)
; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: call foo
; CHECK-NEXT: addi sp, s0, -2032
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload

2
llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
View File

@ -1330,7 +1330,7 @@ define i16 @overflow_not_used(i16 %a, i16 %b, ptr %res) {
; RV64: # %bb.0:
; RV64-NEXT: lui a3, 16
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: addiw a3, a3, -1
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a4, a1, a3
; RV64-NEXT: and a3, a0, a3
; RV64-NEXT: bltu a3, a4, .LBB38_2

8
llvm/test/CodeGen/RISCV/pr135206.ll
View File

@ -42,10 +42,10 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a0, a0, 32
; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addiw a0, a1, 1622
; CHECK-NEXT: addi a0, a1, 1622
; CHECK-NEXT: vse8.v v8, (s0)
; CHECK-NEXT: vse8.v v8, (s1)
; CHECK-NEXT: vse8.v v8, (s2)
@ -54,7 +54,7 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
; CHECK-NEXT: sd s3, 64(sp)
; CHECK-NEXT: call bar
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a0, a0, 32
; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
@ -66,7 +66,7 @@ define i1 @foo() nounwind "probe-stack"="inline-asm" "target-features"="+v" {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addiw a1, a1, -1952
; CHECK-NEXT: addi a1, a1, -1952
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload

8
llvm/test/CodeGen/RISCV/pr56457.ll
View File

@ -14,9 +14,9 @@ define i15 @foo(i15 %x) nounwind {
; CHECK-NEXT: lui a3, 209715
; CHECK-NEXT: lui a4, 61681
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: addiw a1, a2, 1365
; CHECK-NEXT: addiw a2, a3, 819
; CHECK-NEXT: addiw a3, a4, -241
; CHECK-NEXT: addi a1, a2, 1365
; CHECK-NEXT: addi a2, a3, 819
; CHECK-NEXT: addi a3, a4, -241
; CHECK-NEXT: slli a4, a2, 32
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: slli a4, a3, 32
@ -43,7 +43,7 @@ define i15 @foo(i15 %x) nounwind {
; CHECK-NEXT: srli a1, a0, 4
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: lui a1, 4112
; CHECK-NEXT: addiw a1, a1, 257
; CHECK-NEXT: addi a1, a1, 257
; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: slli a2, a1, 32
; CHECK-NEXT: add a1, a1, a2

24
llvm/test/CodeGen/RISCV/pr58286.ll
View File

@ -7,7 +7,7 @@ define void @func() {
; RV64I-LABEL: func:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 4112
; RV64I-NEXT: lui a0, %hi(var)
@ -25,11 +25,11 @@ define void @func() {
; RV64I-NEXT: lw t4, %lo(var)(a0)
; RV64I-NEXT: lw t5, %lo(var)(a0)
; RV64I-NEXT: lw t6, %lo(var)(a0)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui s0, 1
; RV64I-NEXT: add s0, sp, s0
; RV64I-NEXT: sw a1, 12(s0)
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a1, %lo(var)(a0)
; RV64I-NEXT: sw a2, %lo(var)(a0)
; RV64I-NEXT: sw a3, %lo(var)(a0)
@ -45,7 +45,7 @@ define void @func() {
; RV64I-NEXT: sw t5, %lo(var)(a0)
; RV64I-NEXT: sw t6, %lo(var)(a0)
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
@ -71,11 +71,11 @@ define void @func() {
; RV32I-NEXT: lw t4, %lo(var)(a0)
; RV32I-NEXT: lw t5, %lo(var)(a0)
; RV32I-NEXT: lw t6, %lo(var)(a0)
; RV32I-NEXT: sw s0, 0(sp)
; RV32I-NEXT: sw s0, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s0, 1
; RV32I-NEXT: add s0, sp, s0
; RV32I-NEXT: sw a1, 12(s0)
; RV32I-NEXT: lw s0, 0(sp)
; RV32I-NEXT: lw s0, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a1, %lo(var)(a0)
; RV32I-NEXT: sw a2, %lo(var)(a0)
; RV32I-NEXT: sw a3, %lo(var)(a0)
@ -142,7 +142,7 @@ define void @shrink_wrap(i1 %c) {
; RV64I-NEXT: bnez a0, .LBB1_2
; RV64I-NEXT: # %bb.1: # %bar
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 4112
; RV64I-NEXT: lui a0, %hi(var)
@ -160,11 +160,11 @@ define void @shrink_wrap(i1 %c) {
; RV64I-NEXT: lw t4, %lo(var)(a0)
; RV64I-NEXT: lw t5, %lo(var)(a0)
; RV64I-NEXT: lw t6, %lo(var)(a0)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui s0, 1
; RV64I-NEXT: add s0, sp, s0
; RV64I-NEXT: sw a1, 12(s0)
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a1, %lo(var)(a0)
; RV64I-NEXT: sw a2, %lo(var)(a0)
; RV64I-NEXT: sw a3, %lo(var)(a0)
@ -180,7 +180,7 @@ define void @shrink_wrap(i1 %c) {
; RV64I-NEXT: sw t5, %lo(var)(a0)
; RV64I-NEXT: sw t6, %lo(var)(a0)
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: .LBB1_2: # %foo
@ -210,11 +210,11 @@ define void @shrink_wrap(i1 %c) {
; RV32I-NEXT: lw t4, %lo(var)(a0)
; RV32I-NEXT: lw t5, %lo(var)(a0)
; RV32I-NEXT: lw t6, %lo(var)(a0)
; RV32I-NEXT: sw s0, 0(sp)
; RV32I-NEXT: sw s0, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s0, 1
; RV32I-NEXT: add s0, sp, s0
; RV32I-NEXT: sw a1, 12(s0)
; RV32I-NEXT: lw s0, 0(sp)
; RV32I-NEXT: lw s0, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a1, %lo(var)(a0)
; RV32I-NEXT: sw a2, %lo(var)(a0)
; RV32I-NEXT: sw a3, %lo(var)(a0)

8
llvm/test/CodeGen/RISCV/pr58511.ll
View File

@ -7,7 +7,7 @@ define i32 @f(i1 %0, i32 %1, ptr %2) {
; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: lui a3, 4097
; CHECK-NEXT: srai a0, a0, 63
; CHECK-NEXT: addiw a3, a3, -2047
; CHECK-NEXT: addi a3, a3, -2047
; CHECK-NEXT: or a0, a0, a3
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sw a1, 0(a2)
@ -26,7 +26,7 @@ define i32 @g(i1 %0, i32 %1, ptr %2) {
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: lui a3, 4097
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: addiw a3, a3, -2047
; CHECK-NEXT: addi a3, a3, -2047
; CHECK-NEXT: or a0, a0, a3
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sw a1, 0(a2)
@ -44,7 +44,7 @@ define i32 @h(i1 %0, i32 %1, ptr %2) {
; CHECK: # %bb.0: # %BB
; CHECK-NEXT: lui a3, 4097
; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: addiw a3, a3, -2047
; CHECK-NEXT: addi a3, a3, -2047
; CHECK-NEXT: srai a0, a0, 63
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: and a0, a0, a3
@ -63,7 +63,7 @@ define i32 @i(i1 %0, i32 %1, ptr %2) {
; CHECK: # %bb.0: # %BB
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: lui a3, 4097
; CHECK-NEXT: addiw a3, a3, -2047
; CHECK-NEXT: addi a3, a3, -2047
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: and a0, a0, a3

2
llvm/test/CodeGen/RISCV/pr68855.ll
View File

@ -7,7 +7,7 @@ define i16 @narrow_load(ptr %p1, ptr %p2) {
; CHECK-NEXT: lhu a2, 0(a0)
; CHECK-NEXT: lui a3, 2
; CHECK-NEXT: lui a4, 16
; CHECK-NEXT: addiw a3, a3, -1
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: xor a2, a2, a3
; CHECK-NEXT: xor a4, a3, a4

132
llvm/test/CodeGen/RISCV/pr69586.ll
View File

@ -253,7 +253,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v4, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v26, v8
; NOREMAT-NEXT: lui a4, 4
; NOREMAT-NEXT: addiw a0, a4, 512
; NOREMAT-NEXT: addi a0, a4, 512
; NOREMAT-NEXT: sd a0, 496(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a0, a7, a0
; NOREMAT-NEXT: vle32.v v8, (a0)
@ -265,7 +265,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v28, (a2)
; NOREMAT-NEXT: vle32.v v6, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v30, v12
; NOREMAT-NEXT: addiw a2, a4, 1536
; NOREMAT-NEXT: addi a2, a4, 1536
; NOREMAT-NEXT: sd a2, 480(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v12, (a2)
@ -278,7 +278,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v4, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v22, v8
; NOREMAT-NEXT: lui a5, 5
; NOREMAT-NEXT: addiw a2, a5, -1536
; NOREMAT-NEXT: addi a2, a5, -1536
; NOREMAT-NEXT: sd a2, 464(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v8, (a2)
@ -291,13 +291,13 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v26, (a2)
; NOREMAT-NEXT: vle32.v v28, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v6, v12
; NOREMAT-NEXT: addiw a2, a5, -512
; NOREMAT-NEXT: addi a2, a5, -512
; NOREMAT-NEXT: sd a2, 448(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v12, (a2)
; NOREMAT-NEXT: vle32.v v6, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v30, v24
; NOREMAT-NEXT: addiw a2, a5, 512
; NOREMAT-NEXT: addi a2, a5, 512
; NOREMAT-NEXT: sd a2, 440(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v24, (a2)
@ -309,7 +309,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v8, (a2)
; NOREMAT-NEXT: vle32.v v4, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v22, v26
; NOREMAT-NEXT: addiw a2, a5, 1536
; NOREMAT-NEXT: addi a2, a5, 1536
; NOREMAT-NEXT: sd a2, 424(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v22, (a2)
@ -322,7 +322,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v28, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v6, v18
; NOREMAT-NEXT: lui a6, 6
; NOREMAT-NEXT: addiw a2, a6, -1536
; NOREMAT-NEXT: addi a2, a6, -1536
; NOREMAT-NEXT: sd a2, 408(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v18, (a2)
@ -334,13 +334,13 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v16, (a2)
; NOREMAT-NEXT: vle32.v v24, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v30, v8
; NOREMAT-NEXT: addiw a2, a6, -512
; NOREMAT-NEXT: addi a2, a6, -512
; NOREMAT-NEXT: sd a2, 392(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v8, (a2)
; NOREMAT-NEXT: vle32.v v30, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v4, v22
; NOREMAT-NEXT: addiw a2, a6, 512
; NOREMAT-NEXT: addi a2, a6, 512
; NOREMAT-NEXT: sd a2, 384(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v22, (a2)
@ -352,7 +352,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v26, (a2)
; NOREMAT-NEXT: vle32.v v2, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v28, v18
; NOREMAT-NEXT: addiw a2, a6, 1536
; NOREMAT-NEXT: addi a2, a6, 1536
; NOREMAT-NEXT: sd a2, 368(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v18, (a2)
@ -365,7 +365,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v6, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v24, v8
; NOREMAT-NEXT: lui s0, 7
; NOREMAT-NEXT: addiw a2, s0, -1536
; NOREMAT-NEXT: addi a2, s0, -1536
; NOREMAT-NEXT: sd a2, 352(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v8, (a2)
@ -379,13 +379,13 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: addi a0, sp, 640
; NOREMAT-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; NOREMAT-NEXT: sf.vc.vv 3, 0, v12, v22
; NOREMAT-NEXT: addiw a2, s0, -512
; NOREMAT-NEXT: addi a2, s0, -512
; NOREMAT-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v22, (a2)
; NOREMAT-NEXT: vle32.v v12, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v4, v26
; NOREMAT-NEXT: addiw a2, s0, 512
; NOREMAT-NEXT: addi a2, s0, 512
; NOREMAT-NEXT: sd a2, 328(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: lui t3, 7
; NOREMAT-NEXT: add a2, a7, a2
@ -398,7 +398,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v18, (a2)
; NOREMAT-NEXT: vle32.v v2, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v28, v16
; NOREMAT-NEXT: addiw a2, t3, 1536
; NOREMAT-NEXT: addi a2, t3, 1536
; NOREMAT-NEXT: sd a2, 312(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v16, (a2)
@ -410,7 +410,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v8, (a2)
; NOREMAT-NEXT: vle32.v v6, (a2)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v24, v14
; NOREMAT-NEXT: addiw a2, t4, -1536
; NOREMAT-NEXT: addi a2, t4, -1536
; NOREMAT-NEXT: sd a2, 296(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v14, (a2)
@ -421,7 +421,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: add a2, a7, a2
; NOREMAT-NEXT: vle32.v v22, (a2)
; NOREMAT-NEXT: vle32.v v30, (a2)
; NOREMAT-NEXT: addiw a0, t4, -512
; NOREMAT-NEXT: addi a0, t4, -512
; NOREMAT-NEXT: sd a0, 280(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a0, a7, a0
; NOREMAT-NEXT: sf.vc.vv 3, 0, v12, v0
@ -456,34 +456,34 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: sd t3, 224(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a0, a1, t4
; NOREMAT-NEXT: sd a0, 216(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a0, t4, 512
; NOREMAT-NEXT: addi a0, t4, 512
; NOREMAT-NEXT: sd a0, 192(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a0, t4, 1024
; NOREMAT-NEXT: addi a0, t4, 1024
; NOREMAT-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a0, t4, 1536
; NOREMAT-NEXT: addi a0, t4, 1536
; NOREMAT-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: slli s1, s1, 11
; NOREMAT-NEXT: sd s1, 128(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: lui a0, 9
; NOREMAT-NEXT: addiw a2, a0, -1536
; NOREMAT-NEXT: addi a2, a0, -1536
; NOREMAT-NEXT: sd a2, 88(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a2, a0, -1024
; NOREMAT-NEXT: addi a2, a0, -1024
; NOREMAT-NEXT: sd a2, 72(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a2, a0, -512
; NOREMAT-NEXT: addi a2, a0, -512
; NOREMAT-NEXT: sd a2, 40(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: add a2, a1, a0
; NOREMAT-NEXT: sd a2, 208(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw s11, a0, 512
; NOREMAT-NEXT: addiw s7, a0, 1024
; NOREMAT-NEXT: addiw s3, a0, 1536
; NOREMAT-NEXT: addi s11, a0, 512
; NOREMAT-NEXT: addi s7, a0, 1024
; NOREMAT-NEXT: addi s3, a0, 1536
; NOREMAT-NEXT: slli s1, t2, 11
; NOREMAT-NEXT: lui a0, 10
; NOREMAT-NEXT: addiw t2, a0, -1536
; NOREMAT-NEXT: addiw a7, a0, -1024
; NOREMAT-NEXT: addiw a4, a0, -512
; NOREMAT-NEXT: addi t2, a0, -1536
; NOREMAT-NEXT: addi a7, a0, -1024
; NOREMAT-NEXT: addi a4, a0, -512
; NOREMAT-NEXT: add a2, a1, a0
; NOREMAT-NEXT: sd a2, 200(sp) # 8-byte Folded Spill
; NOREMAT-NEXT: addiw a0, a0, 512
; NOREMAT-NEXT: addi a0, a0, 512
; NOREMAT-NEXT: ld a2, 512(sp) # 8-byte Folded Reload
; NOREMAT-NEXT: add a2, a1, a2
; NOREMAT-NEXT: ld a3, 504(sp) # 8-byte Folded Reload
@ -1195,7 +1195,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: lui a2, 4
; REMAT-NEXT: addiw a2, a2, 512
; REMAT-NEXT: addi a2, a2, 512
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v2, (a2)
; REMAT-NEXT: csrr a3, vlenb
@ -1217,7 +1217,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v14
; REMAT-NEXT: vle32.v v22, (a2)
; REMAT-NEXT: lui a2, 4
; REMAT-NEXT: addiw a2, a2, 1536
; REMAT-NEXT: addi a2, a2, 1536
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v24, (a2)
; REMAT-NEXT: csrr a3, vlenb
@ -1242,7 +1242,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v18
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: lui a2, 5
; REMAT-NEXT: addiw a2, a2, -1536
; REMAT-NEXT: addi a2, a2, -1536
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v28, (a2)
; REMAT-NEXT: csrr a3, vlenb
@ -1266,7 +1266,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: lui a2, 5
; REMAT-NEXT: addiw a2, a2, -512
; REMAT-NEXT: addi a2, a2, -512
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v6, (a2)
; REMAT-NEXT: csrr a3, vlenb
@ -1288,7 +1288,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v18, v2
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: lui a2, 5
; REMAT-NEXT: addiw a2, a2, 512
; REMAT-NEXT: addi a2, a2, 512
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v2, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v20, v0
@ -1300,7 +1300,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v22, v24
; REMAT-NEXT: vle32.v v22, (a2)
; REMAT-NEXT: lui s4, 5
; REMAT-NEXT: addiw s4, s4, 1536
; REMAT-NEXT: addi s4, s4, 1536
; REMAT-NEXT: add a2, a0, s4
; REMAT-NEXT: vle32.v v24, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v26
@ -1312,7 +1312,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v28
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: lui s3, 6
; REMAT-NEXT: addiw s3, s3, -1536
; REMAT-NEXT: addi s3, s3, -1536
; REMAT-NEXT: add a2, a0, s3
; REMAT-NEXT: vle32.v v28, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v30
@ -1324,7 +1324,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: lui a2, 6
; REMAT-NEXT: addiw a2, a2, -512
; REMAT-NEXT: addi a2, a2, -512
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v6, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
@ -1336,7 +1336,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v18, v2
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: lui s0, 6
; REMAT-NEXT: addiw s0, s0, 512
; REMAT-NEXT: addi s0, s0, 512
; REMAT-NEXT: add a2, a0, s0
; REMAT-NEXT: vle32.v v2, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v20, v0
@ -1348,7 +1348,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v22, v24
; REMAT-NEXT: vle32.v v22, (a2)
; REMAT-NEXT: lui t6, 6
; REMAT-NEXT: addiw t6, t6, 1536
; REMAT-NEXT: addi t6, t6, 1536
; REMAT-NEXT: add a2, a0, t6
; REMAT-NEXT: vle32.v v24, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v26
@ -1360,7 +1360,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v28
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: lui a2, 7
; REMAT-NEXT: addiw a2, a2, -1536
; REMAT-NEXT: addi a2, a2, -1536
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v28, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v30
@ -1372,7 +1372,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: lui a2, 7
; REMAT-NEXT: addiw a2, a2, -512
; REMAT-NEXT: addi a2, a2, -512
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v6, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
@ -1384,7 +1384,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v18, v2
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: lui t2, 7
; REMAT-NEXT: addiw t2, t2, 512
; REMAT-NEXT: addi t2, t2, 512
; REMAT-NEXT: add a2, a0, t2
; REMAT-NEXT: vle32.v v2, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v20, v0
@ -1396,7 +1396,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v22, v24
; REMAT-NEXT: vle32.v v22, (a2)
; REMAT-NEXT: lui t0, 7
; REMAT-NEXT: addiw t0, t0, 1536
; REMAT-NEXT: addi t0, t0, 1536
; REMAT-NEXT: add a2, a0, t0
; REMAT-NEXT: vle32.v v24, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v26
@ -1408,7 +1408,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v28
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: lui a6, 8
; REMAT-NEXT: addiw a6, a6, -1536
; REMAT-NEXT: addi a6, a6, -1536
; REMAT-NEXT: add a2, a0, a6
; REMAT-NEXT: vle32.v v28, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v30
@ -1420,7 +1420,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: lui a3, 8
; REMAT-NEXT: addiw a3, a3, -512
; REMAT-NEXT: addi a3, a3, -512
; REMAT-NEXT: add a2, a0, a3
; REMAT-NEXT: vle32.v v6, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
@ -1537,7 +1537,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 192(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 4
; REMAT-NEXT: addiw a0, a0, 512
; REMAT-NEXT: addi a0, a0, 512
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 184(sp) # 8-byte Folded Spill
; REMAT-NEXT: li a0, 17
@ -1545,7 +1545,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 4
; REMAT-NEXT: addiw a0, a0, 1536
; REMAT-NEXT: addi a0, a0, 1536
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
; REMAT-NEXT: li a0, 9
@ -1553,7 +1553,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 5
; REMAT-NEXT: addiw a0, a0, -1536
; REMAT-NEXT: addi a0, a0, -1536
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
; REMAT-NEXT: li a0, 19
@ -1561,14 +1561,14 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 5
; REMAT-NEXT: addiw a0, a0, -512
; REMAT-NEXT: addi a0, a0, -512
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 5
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 5
; REMAT-NEXT: addiw a0, a0, 512
; REMAT-NEXT: addi a0, a0, 512
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
; REMAT-NEXT: add s7, a1, s7
@ -1584,7 +1584,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add s2, a1, s2
; REMAT-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 6
; REMAT-NEXT: addiw a0, a0, -512
; REMAT-NEXT: addi a0, a0, -512
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
; REMAT-NEXT: add s1, a1, s1
@ -1600,13 +1600,13 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add t5, a1, t5
; REMAT-NEXT: sd t5, 32(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui a0, 7
; REMAT-NEXT: addiw a0, a0, -1536
; REMAT-NEXT: addi a0, a0, -1536
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; REMAT-NEXT: add t4, a1, t4
; REMAT-NEXT: sd t4, 16(sp) # 8-byte Folded Spill
; REMAT-NEXT: lui ra, 7
; REMAT-NEXT: addiw ra, ra, -512
; REMAT-NEXT: addi ra, ra, -512
; REMAT-NEXT: add ra, a1, ra
; REMAT-NEXT: add s11, a1, t3
; REMAT-NEXT: add s10, a1, t2
@ -1618,53 +1618,53 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: add s4, a1, a3
; REMAT-NEXT: add s3, a1, a2
; REMAT-NEXT: lui s2, 8
; REMAT-NEXT: addiw s2, s2, 512
; REMAT-NEXT: addi s2, s2, 512
; REMAT-NEXT: add s2, a1, s2
; REMAT-NEXT: lui s1, 8
; REMAT-NEXT: addiw s1, s1, 1024
; REMAT-NEXT: addi s1, s1, 1024
; REMAT-NEXT: add s1, a1, s1
; REMAT-NEXT: lui s0, 8
; REMAT-NEXT: addiw s0, s0, 1536
; REMAT-NEXT: addi s0, s0, 1536
; REMAT-NEXT: add s0, a1, s0
; REMAT-NEXT: li t6, 17
; REMAT-NEXT: slli t6, t6, 11
; REMAT-NEXT: add t6, a1, t6
; REMAT-NEXT: lui t5, 9
; REMAT-NEXT: addiw t5, t5, -1536
; REMAT-NEXT: addi t5, t5, -1536
; REMAT-NEXT: add t5, a1, t5
; REMAT-NEXT: lui t4, 9
; REMAT-NEXT: addiw t4, t4, -1024
; REMAT-NEXT: addi t4, t4, -1024
; REMAT-NEXT: add t4, a1, t4
; REMAT-NEXT: lui t3, 9
; REMAT-NEXT: addiw t3, t3, -512
; REMAT-NEXT: addi t3, t3, -512
; REMAT-NEXT: add t3, a1, t3
; REMAT-NEXT: lui t2, 9
; REMAT-NEXT: add t2, a1, t2
; REMAT-NEXT: lui t1, 9
; REMAT-NEXT: addiw t1, t1, 512
; REMAT-NEXT: addi t1, t1, 512
; REMAT-NEXT: add t1, a1, t1
; REMAT-NEXT: lui t0, 9
; REMAT-NEXT: addiw t0, t0, 1024
; REMAT-NEXT: addi t0, t0, 1024
; REMAT-NEXT: add t0, a1, t0
; REMAT-NEXT: lui a7, 9
; REMAT-NEXT: addiw a7, a7, 1536
; REMAT-NEXT: addi a7, a7, 1536
; REMAT-NEXT: add a7, a1, a7
; REMAT-NEXT: li a6, 19
; REMAT-NEXT: slli a6, a6, 11
; REMAT-NEXT: add a6, a1, a6
; REMAT-NEXT: lui a5, 10
; REMAT-NEXT: addiw a5, a5, -1536
; REMAT-NEXT: addi a5, a5, -1536
; REMAT-NEXT: add a5, a1, a5
; REMAT-NEXT: lui a4, 10
; REMAT-NEXT: addiw a4, a4, -1024
; REMAT-NEXT: addi a4, a4, -1024
; REMAT-NEXT: add a4, a1, a4
; REMAT-NEXT: lui a3, 10
; REMAT-NEXT: addiw a3, a3, -512
; REMAT-NEXT: addi a3, a3, -512
; REMAT-NEXT: add a3, a1, a3
; REMAT-NEXT: lui a2, 10
; REMAT-NEXT: add a2, a1, a2
; REMAT-NEXT: lui a0, 10
; REMAT-NEXT: addiw a0, a0, 512
; REMAT-NEXT: addi a0, a0, 512
; REMAT-NEXT: add a0, a1, a0
; REMAT-NEXT: addi a1, a1, 1536
; REMAT-NEXT: sf.vc.v.i 2, 0, v8, 0

2
llvm/test/CodeGen/RISCV/pr90730.ll
View File

@ -5,7 +5,7 @@ define i32 @pr90730(i32 %x, i1 %y, ptr %p) {
; CHECK-LABEL: pr90730:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addiw a1, a1, -960
; CHECK-NEXT: addi a1, a1, -960
; CHECK-NEXT: andn a0, a1, a0
; CHECK-NEXT: sw zero, 0(a2)
; CHECK-NEXT: ret

4
llvm/test/CodeGen/RISCV/pr95271.ll
View File

@ -34,12 +34,12 @@ define i32 @PR95271(ptr %p) {
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a0, 1
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2

2
llvm/test/CodeGen/RISCV/prefer-w-inst.ll
View File

@ -17,7 +17,7 @@ define i32 @addiw(i32 %a) {
; NO-STRIP-LABEL: addiw:
; NO-STRIP: # %bb.0:
; NO-STRIP-NEXT: lui a1, 1
; NO-STRIP-NEXT: addiw a1, a1, -1
; NO-STRIP-NEXT: addi a1, a1, -1
; NO-STRIP-NEXT: addw a0, a0, a1
; NO-STRIP-NEXT: ret
;

20
llvm/test/CodeGen/RISCV/prefetch.ll
View File

@ -715,10 +715,10 @@ define void @test_prefetch_frameindex_1() nounwind {
; RV64I-LABEL: test_prefetch_frameindex_1:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: ret
;
@ -737,25 +737,25 @@ define void @test_prefetch_frameindex_1() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_1:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1
; RV64ZICBOP-NEXT: addiw a0, a0, 16
; RV64ZICBOP-NEXT: addi a0, a0, 16
; RV64ZICBOP-NEXT: sub sp, sp, a0
; RV64ZICBOP-NEXT: addi a0, sp, 16
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: lui a0, 1
; RV64ZICBOP-NEXT: addiw a0, a0, 16
; RV64ZICBOP-NEXT: addi a0, a0, 16
; RV64ZICBOP-NEXT: add sp, sp, a0
; RV64ZICBOP-NEXT: ret
;
; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_1:
; RV64ZICBOPZIHINTNTL: # %bb.0:
; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 16
; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
; RV64ZICBOPZIHINTNTL-NEXT: sub sp, sp, a0
; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 16
; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
; RV64ZICBOPZIHINTNTL-NEXT: add sp, sp, a0
; RV64ZICBOPZIHINTNTL-NEXT: ret
%data = alloca [1024 x i32], align 4
@ -1158,14 +1158,14 @@ define void @test_prefetch_constant_address_1() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_constant_address_1:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1
; RV64ZICBOP-NEXT: addiw a0, a0, 31
; RV64ZICBOP-NEXT: addi a0, a0, 31
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_1:
; RV64ZICBOPZIHINTNTL: # %bb.0:
; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 31
; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
; RV64ZICBOPZIHINTNTL-NEXT: ret
@ -1225,14 +1225,14 @@ define void @test_prefetch_constant_address_3() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_constant_address_3:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1048561
; RV64ZICBOP-NEXT: addiw a0, a0, 31
; RV64ZICBOP-NEXT: addi a0, a0, 31
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_3:
; RV64ZICBOPZIHINTNTL: # %bb.0:
; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 31
; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
; RV64ZICBOPZIHINTNTL-NEXT: ret

12
llvm/test/CodeGen/RISCV/prolog-epilogue.ll
View File

@ -257,13 +257,13 @@ define void @frame_4kb_offset_128() {
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 6256
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
@ -393,13 +393,13 @@ define void @frame_8kb_offset_128() {
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 10352
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee
; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
@ -482,13 +482,13 @@ define void @frame_16kb_minus_80() {
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: addiw a0, a0, -80
; RV64I-NEXT: addi a0, a0, -80
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 18336
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee
; RV64I-NEXT: lui a0, 4
; RV64I-NEXT: addiw a0, a0, -80
; RV64I-NEXT: addi a0, a0, -80
; RV64I-NEXT: add sp, sp, a0
; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload

2
llvm/test/CodeGen/RISCV/rem.ll
View File

@ -567,7 +567,7 @@ define i16 @urem16(i16 %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: call __umoddi3

2
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
View File

@ -51,7 +51,7 @@ define half @half_test(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: addi s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s1, a0

8
llvm/test/CodeGen/RISCV/rv64-float-convert.ll
View File

@ -83,7 +83,7 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64I-NEXT: slli s3, s5, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: lui a1, 520192
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: mv s4, a0
@ -168,7 +168,7 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
; RV64IZFINX-NEXT: slli a1, a2, 63
; RV64IZFINX-NEXT: .LBB4_2:
; RV64IZFINX-NEXT: lui a3, 520192
; RV64IZFINX-NEXT: addiw a3, a3, -1
; RV64IZFINX-NEXT: addi a3, a3, -1
; RV64IZFINX-NEXT: flt.s a3, a3, s0
; RV64IZFINX-NEXT: beqz a3, .LBB4_4
; RV64IZFINX-NEXT: # %bb.3:
@ -202,7 +202,7 @@ define i128 @fptoui_sat_f32_to_i128(float %a) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 522240
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: neg s1, a0
@ -263,7 +263,7 @@ define i128 @fptoui_sat_f32_to_i128(float %a) nounwind {
; RV64IZFINX-NEXT: and a0, s1, a0
; RV64IZFINX-NEXT: lui a2, 522240
; RV64IZFINX-NEXT: and a1, s1, a1
; RV64IZFINX-NEXT: addiw a2, a2, -1
; RV64IZFINX-NEXT: addi a2, a2, -1
; RV64IZFINX-NEXT: flt.s a2, a2, s0
; RV64IZFINX-NEXT: neg a2, a2
; RV64IZFINX-NEXT: or a0, a2, a0

8
llvm/test/CodeGen/RISCV/rv64-half-convert.ll
View File

@ -160,7 +160,7 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-NEXT: slli s3, s5, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: lui a1, 520192
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: mv s4, a0
@ -246,7 +246,7 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64IZHINX-NEXT: slli a1, a2, 63
; RV64IZHINX-NEXT: .LBB4_2:
; RV64IZHINX-NEXT: lui a3, 520192
; RV64IZHINX-NEXT: addiw a3, a3, -1
; RV64IZHINX-NEXT: addi a3, a3, -1
; RV64IZHINX-NEXT: flt.s a3, a3, s0
; RV64IZHINX-NEXT: beqz a3, .LBB4_4
; RV64IZHINX-NEXT: # %bb.3:
@ -281,7 +281,7 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 522240
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: neg s1, a0
@ -336,7 +336,7 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 522240
; RV64IZHINX-NEXT: addiw a1, a1, -1
; RV64IZHINX-NEXT: addi a1, a1, -1
; RV64IZHINX-NEXT: fle.s a2, zero, a0
; RV64IZHINX-NEXT: flt.s a1, a1, a0
; RV64IZHINX-NEXT: neg s0, a1

4
llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
View File

@ -15,7 +15,7 @@ define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: lui ra, 3563
; CHECK-NEXT: addiw ra, ra, -577
; CHECK-NEXT: addi ra, ra, -577
; CHECK-NEXT: slli ra, ra, 12
; CHECK-NEXT: addi ra, ra, -259
; CHECK-NEXT: slli ra, ra, 12
@ -26,7 +26,7 @@ define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: lui ra, 3563
; CHECK-NEXT: addiw ra, ra, -577
; CHECK-NEXT: addi ra, ra, -577
; CHECK-NEXT: slli ra, ra, 12
; CHECK-NEXT: addi ra, ra, -259
; CHECK-NEXT: slli ra, ra, 12

12
llvm/test/CodeGen/RISCV/rv64-trampoline.ll
View File

@ -21,13 +21,13 @@ define i64 @test0(i64 %n, ptr %p) nounwind {
; RV64-NEXT: li a0, 919
; RV64-NEXT: sw a0, 24(sp)
; RV64-NEXT: lui a0, 40
; RV64-NEXT: addiw a0, a0, 103
; RV64-NEXT: addi a0, a0, 103
; RV64-NEXT: sw a0, 36(sp)
; RV64-NEXT: lui a0, 4155
; RV64-NEXT: addiw a0, a0, 899
; RV64-NEXT: addi a0, a0, 899
; RV64-NEXT: sw a0, 32(sp)
; RV64-NEXT: lui a0, 6203
; RV64-NEXT: addiw a0, a0, 643
; RV64-NEXT: addi a0, a0, 643
; RV64-NEXT: sw a0, 28(sp)
; RV64-NEXT: addi a1, sp, 40
; RV64-NEXT: addi a0, sp, 24
@ -52,13 +52,13 @@ define i64 @test0(i64 %n, ptr %p) nounwind {
; RV64-LINUX-NEXT: li a0, 919
; RV64-LINUX-NEXT: sw a0, 24(sp)
; RV64-LINUX-NEXT: lui a0, 40
; RV64-LINUX-NEXT: addiw a0, a0, 103
; RV64-LINUX-NEXT: addi a0, a0, 103
; RV64-LINUX-NEXT: sw a0, 36(sp)
; RV64-LINUX-NEXT: lui a0, 4155
; RV64-LINUX-NEXT: addiw a0, a0, 899
; RV64-LINUX-NEXT: addi a0, a0, 899
; RV64-LINUX-NEXT: sw a0, 32(sp)
; RV64-LINUX-NEXT: lui a0, 6203
; RV64-LINUX-NEXT: addiw a0, a0, 643
; RV64-LINUX-NEXT: addi a0, a0, 643
; RV64-LINUX-NEXT: sw a0, 28(sp)
; RV64-LINUX-NEXT: addi a1, sp, 40
; RV64-LINUX-NEXT: addi a0, sp, 24

8
llvm/test/CodeGen/RISCV/rv64xtheadba.ll
View File

@ -507,7 +507,7 @@ define i64 @addmul4230(i64 %a, i64 %b) {
; CHECK-LABEL: addmul4230:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: addiw a2, a2, 134
; CHECK-NEXT: addi a2, a2, 134
; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ret
@ -1034,7 +1034,7 @@ define i64 @add4104(i64 %a) {
; RV64I-LABEL: add4104:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: addi a1, a1, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@ -1051,7 +1051,7 @@ define i64 @add4104_2(i64 %a) {
; RV64I-LABEL: add4104_2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: addi a1, a1, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -1068,7 +1068,7 @@ define i64 @add8208(i64 %a) {
; RV64I-LABEL: add8208:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 2
; RV64I-NEXT: addiw a1, a1, 16
; RV64I-NEXT: addi a1, a1, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;

30
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
View File

@ -14,7 +14,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -27,7 +27,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -66,7 +66,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -79,7 +79,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -127,7 +127,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a2, a1, 1
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: addiw a2, a3, 1365
; RV64I-NEXT: addi a2, a3, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
@ -140,7 +140,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
@ -181,7 +181,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a1, a0, a1
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
@ -194,7 +194,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
@ -242,7 +242,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -255,7 +255,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -299,8 +299,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
@ -319,7 +319,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -849,7 +849,7 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a1, a3
@ -905,7 +905,7 @@ define i64 @bswap_i64(i64 %a) {
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 8

10
llvm/test/CodeGen/RISCV/rv64zba.ll
View File

@ -1049,7 +1049,7 @@ define i64 @addmul4230(i64 %a, i64 %b) {
; CHECK-LABEL: addmul4230:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: addiw a2, a2, 134
; CHECK-NEXT: addi a2, a2, 134
; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ret
@ -2061,7 +2061,7 @@ define i64 @add4104(i64 %a) {
; RV64I-LABEL: add4104:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: addi a1, a1, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@ -2084,7 +2084,7 @@ define i64 @add4104_2(i64 %a) {
; RV64I-LABEL: add4104_2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 8
; RV64I-NEXT: addi a1, a1, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -2107,7 +2107,7 @@ define i64 @add8208(i64 %a) {
; RV64I-LABEL: add8208:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 2
; RV64I-NEXT: addiw a1, a1, 16
; RV64I-NEXT: addi a1, a1, 16
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
@ -4099,7 +4099,7 @@ define i64 @srli_slli_i16(i64 %1) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: lui a1, 256
; CHECK-NEXT: addiw a1, a1, -16
; CHECK-NEXT: addi a1, a1, -16
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: ret
entry:

2
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
View File

@ -62,7 +62,7 @@ define i64 @orcb64_knownbits(i64 %a) nounwind {
; RV64ZBB-NEXT: lui a1, 65535
; RV64ZBB-NEXT: lui a2, 4080
; RV64ZBB-NEXT: slli a1, a1, 12
; RV64ZBB-NEXT: addiw a2, a2, 255
; RV64ZBB-NEXT: addi a2, a2, 255
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: slli a1, a2, 40
; RV64ZBB-NEXT: orc.b a0, a0

78
llvm/test/CodeGen/RISCV/rv64zbb.ll
View File

@ -14,7 +14,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -27,7 +27,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -64,7 +64,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -77,7 +77,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -123,7 +123,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a2, a1, 1
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: addiw a2, a3, 1365
; RV64I-NEXT: addi a2, a3, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
@ -136,7 +136,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
@ -175,7 +175,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a1, a0, a1
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: srliw a3, a1, 2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srliw a3, a1, 4
@ -188,7 +188,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a3, a1, 1
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: addiw a3, a3, 819
; RV64I-NEXT: addi a3, a3, 819
; RV64I-NEXT: sub a1, a1, a2
; RV64I-NEXT: and a2, a1, a3
; RV64I-NEXT: srli a1, a1, 2
@ -234,7 +234,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: srliw a2, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: srliw a2, a0, 4
@ -247,7 +247,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -289,8 +289,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: addi a1, a2, 1365
; RV64I-NEXT: addi a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
@ -309,7 +309,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -567,10 +567,10 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -677,11 +677,11 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: srli a2, a0, 1
; RV64I-NEXT: and a1, a2, a1
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -718,11 +718,11 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind {
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: lui a4, 209715
; RV64I-NEXT: srli a5, a1, 1
; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: and a3, a5, a3
; RV64I-NEXT: lui a5, 61681
; RV64I-NEXT: addiw a4, a4, 819
; RV64I-NEXT: addi a4, a4, 819
; RV64I-NEXT: addi a5, a5, -241
; RV64I-NEXT: sub a0, a0, a2
; RV64I-NEXT: sub a1, a1, a3
@ -876,8 +876,8 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: slli a3, a1, 32
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a2, 32
@ -885,7 +885,7 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
@ -998,9 +998,9 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV64I-NEXT: lui a3, 349525
; RV64I-NEXT: lui a4, 209715
; RV64I-NEXT: lui a5, 61681
; RV64I-NEXT: addiw a3, a3, 1365
; RV64I-NEXT: addiw a4, a4, 819
; RV64I-NEXT: addiw a5, a5, -241
; RV64I-NEXT: addi a3, a3, 1365
; RV64I-NEXT: addi a4, a4, 819
; RV64I-NEXT: addi a5, a5, -241
; RV64I-NEXT: slli a6, a3, 32
; RV64I-NEXT: add a3, a3, a6
; RV64I-NEXT: slli a6, a4, 32
@ -1453,7 +1453,7 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a1, a3
@ -1511,7 +1511,7 @@ define i64 @bswap_i64(i64 %a) {
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: srli a4, a0, 24
; RV64I-NEXT: lui a5, 4080
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: addi a2, a2, -256
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 8
@ -1572,7 +1572,7 @@ define i32 @orc_b_i32(i32 %a) {
; RV64ZBB-LABEL: orc_b_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, 4112
; RV64ZBB-NEXT: addiw a1, a1, 257
; RV64ZBB-NEXT: addi a1, a1, 257
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: orc.b a0, a0
; RV64ZBB-NEXT: ret
@ -1585,7 +1585,7 @@ define i64 @orc_b_i64(i64 %a) {
; RV64I-LABEL: orc_b_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: and a0, a0, a1
@ -1596,7 +1596,7 @@ define i64 @orc_b_i64(i64 %a) {
; RV64ZBB-LABEL: orc_b_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, 4112
; RV64ZBB-NEXT: addiw a1, a1, 257
; RV64ZBB-NEXT: addi a1, a1, 257
; RV64ZBB-NEXT: slli a2, a1, 32
; RV64ZBB-NEXT: add a1, a1, a2
; RV64ZBB-NEXT: and a0, a0, a1
@ -1755,7 +1755,7 @@ define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
; RV64I-LABEL: sub_if_uge_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a3, a1, a2
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: sltu a2, a2, a3
@ -1978,7 +1978,7 @@ define i32 @sub_if_uge_C_i32(i32 signext %x) {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: addiw a1, a1, -16
; RV64I-NEXT: addi a1, a1, -16
; RV64I-NEXT: sltu a1, a1, a0
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: addi a2, a2, 15
@ -2004,8 +2004,8 @@ define i64 @sub_if_uge_C_i64(i64 %x) {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 298
; RV64I-NEXT: lui a2, 1046192
; RV64I-NEXT: addiw a1, a1, 95
; RV64I-NEXT: addiw a2, a2, -761
; RV64I-NEXT: addi a1, a1, 95
; RV64I-NEXT: addi a2, a2, -761
; RV64I-NEXT: slli a1, a1, 12
; RV64I-NEXT: addi a1, a1, 511
; RV64I-NEXT: sltu a1, a1, a0
@ -2018,7 +2018,7 @@ define i64 @sub_if_uge_C_i64(i64 %x) {
; RV64ZBB-LABEL: sub_if_uge_C_i64:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a1, 1046192
; RV64ZBB-NEXT: addiw a1, a1, -761
; RV64ZBB-NEXT: addi a1, a1, -761
; RV64ZBB-NEXT: slli a1, a1, 9
; RV64ZBB-NEXT: add a1, a0, a1
; RV64ZBB-NEXT: minu a0, a1, a0
@ -2034,7 +2034,7 @@ define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: lui a3, 1048560
; RV64I-NEXT: addiw a2, a2, -16
; RV64I-NEXT: addi a2, a2, -16
; RV64I-NEXT: sltu a2, a2, a0
; RV64I-NEXT: negw a4, a2
; RV64I-NEXT: addi a3, a3, 15
@ -2047,7 +2047,7 @@ define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: lui a2, 16
; RV64ZBB-NEXT: lui a3, 1048560
; RV64ZBB-NEXT: addiw a2, a2, -16
; RV64ZBB-NEXT: addi a2, a2, -16
; RV64ZBB-NEXT: addi a3, a3, 15
; RV64ZBB-NEXT: sltu a2, a2, a0
; RV64ZBB-NEXT: addw a3, a0, a3
@ -2069,7 +2069,7 @@ define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addi a2, a2, 15
; RV64I-NEXT: addw a2, a0, a2
; RV64I-NEXT: addiw a3, a3, -16
; RV64I-NEXT: addi a3, a3, -16
; RV64I-NEXT: sw a2, 0(a1)
; RV64I-NEXT: bltu a3, a0, .LBB75_2
; RV64I-NEXT: # %bb.1:
@ -2098,7 +2098,7 @@ define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: addiw a1, a1, -15
; RV64I-NEXT: addi a1, a1, -15
; RV64I-NEXT: sltu a1, a0, a1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addi a2, a2, 15

2
llvm/test/CodeGen/RISCV/rv64zbkb.ll
View File

@ -319,7 +319,7 @@ define i64 @pack_i64_imm() {
; RV64I-LABEL: pack_i64_imm:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 65793
; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: addi a0, a0, 16
; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret

22
llvm/test/CodeGen/RISCV/rv64zbs.ll
View File

@ -513,7 +513,7 @@ define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -529,7 +529,7 @@ define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -564,7 +564,7 @@ define i64 @bclri_i64_11(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -580,7 +580,7 @@ define i64 @bclri_i64_30(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -644,7 +644,7 @@ define i64 @bclri_i64_large0(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large0:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: addiw a1, a1, -256
; RV64I-NEXT: addi a1, a1, -256
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -661,7 +661,7 @@ define i64 @bclri_i64_large1(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large1:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044464
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
@ -972,7 +972,7 @@ define i64 @xor_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: addi a1, a1, 3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
@ -1016,7 +1016,7 @@ define i64 @xor_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
@ -1033,7 +1033,7 @@ define i64 @or_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: or_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: addi a1, a1, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -1059,7 +1059,7 @@ define i64 @or_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: or_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -1203,7 +1203,7 @@ define i1 @icmp_eq_nonpow2(i32 signext %x) nounwind {
; CHECK-LABEL: icmp_eq_nonpow2:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addiw a1, a1, -1
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret

32
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
View File

@ -782,7 +782,7 @@ define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: vsrl.vx v11, v8, a0
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v11, v11, a2
; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsrl.vi v11, v8, 8
@ -801,9 +801,9 @@ define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) {
; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsll.vx v11, v8, a1
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 819
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 819
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: slli a2, a3, 32
; RV64-NEXT: vsll.vx v8, v8, a0
@ -923,7 +923,7 @@ define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: vsrl.vx v14, v8, a0
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v14, v14, a2
; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsrl.vi v14, v8, 8
@ -942,9 +942,9 @@ define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) {
; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsll.vx v14, v8, a1
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 819
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 819
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: slli a2, a3, 32
; RV64-NEXT: vsll.vx v8, v8, a0
@ -1064,7 +1064,7 @@ define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: vsrl.vx v20, v8, a0
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v20, v20, a2
; RV64-NEXT: vor.vv v12, v20, v12
; RV64-NEXT: vsrl.vi v20, v8, 8
@ -1083,9 +1083,9 @@ define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) {
; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vsll.vx v20, v8, a1
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 819
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 819
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: slli a2, a3, 32
; RV64-NEXT: vsll.vx v8, v8, a0
@ -1227,7 +1227,7 @@ define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v16, v8, a1
; RV64-NEXT: vsrl.vx v0, v8, a0
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
; RV64-NEXT: vsrl.vi v0, v8, 8
@ -1246,9 +1246,9 @@ define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) {
; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vsll.vx v0, v8, a1
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 819
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 819
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: slli a2, a3, 32
; RV64-NEXT: vsll.vx v8, v8, a0

80
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
View File

@ -1512,9 +1512,9 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -1525,7 +1525,7 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
; RV64-NEXT: vand.vx v10, v8, a3, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
@ -1653,7 +1653,7 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v11, v8, a3
; RV64-NEXT: vsrl.vx v12, v8, a5
; RV64-NEXT: vand.vx v12, v12, a0
@ -1674,9 +1674,9 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -1794,9 +1794,9 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -1807,7 +1807,7 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
; RV64-NEXT: vand.vx v12, v8, a3, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
@ -1935,7 +1935,7 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v10, v8, a3
; RV64-NEXT: vsrl.vx v16, v8, a5
; RV64-NEXT: vand.vx v16, v16, a0
@ -1956,9 +1956,9 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2076,9 +2076,9 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -2089,7 +2089,7 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
; RV64-NEXT: vand.vx v16, v8, a3, v0.t
; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
@ -2217,7 +2217,7 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v12, v8, a3
; RV64-NEXT: vsrl.vx v24, v8, a5
; RV64-NEXT: vand.vx v24, v24, a0
@ -2238,9 +2238,9 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2414,7 +2414,7 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -2441,9 +2441,9 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2593,7 +2593,7 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -2617,9 +2617,9 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2801,7 +2801,7 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -2828,9 +2828,9 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2980,7 +2980,7 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -3004,9 +3004,9 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3

8
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
View File

@ -304,7 +304,7 @@ define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vsrl.vx v11, v8, a1
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v11, v11, a2
; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsrl.vi v11, v8, 8
@ -388,7 +388,7 @@ define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vsrl.vx v14, v8, a1
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v14, v14, a2
; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsrl.vi v14, v8, 8
@ -472,7 +472,7 @@ define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vsrl.vx v20, v8, a1
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v20, v20, a2
; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vsrl.vi v20, v8, 8
@ -578,7 +578,7 @@ define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {
; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vsrl.vx v0, v8, a1
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: addi a2, a2, -256
; RV64-NEXT: vand.vx v0, v0, a2
; RV64-NEXT: vor.vv v16, v0, v16
; RV64-NEXT: vsrl.vi v0, v8, 8

22
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
View File

@ -559,7 +559,7 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
@ -642,7 +642,7 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v11, v8, a3
; RV64-NEXT: vsrl.vx v12, v8, a5
; RV64-NEXT: vand.vx v12, v12, a0
@ -727,7 +727,7 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
; RV64-NEXT: vand.vx v12, v8, a2, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
@ -810,7 +810,7 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vsrl.vi v12, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v14, v8, a3
; RV64-NEXT: vsrl.vx v16, v8, a5
; RV64-NEXT: vand.vx v16, v16, a0
@ -895,7 +895,7 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
; RV64-NEXT: vand.vx v16, v8, a2, v0.t
; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
@ -978,7 +978,7 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vi v16, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v20, v8, a3
; RV64-NEXT: vsrl.vx v24, v8, a5
; RV64-NEXT: vand.vx v24, v24, a0
@ -1118,7 +1118,7 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -1239,7 +1239,7 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -1390,7 +1390,7 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -1511,7 +1511,7 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -1709,7 +1709,7 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t

64
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
View File

@ -1189,10 +1189,10 @@ define <vscale x 1 x i64> @ctlz_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1329,10 +1329,10 @@ define <vscale x 2 x i64> @ctlz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1469,10 +1469,10 @@ define <vscale x 4 x i64> @ctlz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1609,10 +1609,10 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -2791,10 +2791,10 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -2925,10 +2925,10 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -3059,10 +3059,10 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -3193,10 +3193,10 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32

32
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
View File

@ -717,10 +717,10 @@ define <vscale x 1 x i64> @ctpop_nxv1i64(<vscale x 1 x i64> %va) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -800,10 +800,10 @@ define <vscale x 2 x i64> @ctpop_nxv2i64(<vscale x 2 x i64> %va) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -883,10 +883,10 @@ define <vscale x 4 x i64> @ctpop_nxv4i64(<vscale x 4 x i64> %va) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -966,10 +966,10 @@ define <vscale x 8 x i64> @ctpop_nxv8i64(<vscale x 8 x i64> %va) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32

96
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
View File

@ -1227,10 +1227,10 @@ define <vscale x 1 x i64> @vp_ctpop_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1309,10 +1309,10 @@ define <vscale x 1 x i64> @vp_ctpop_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1393,10 +1393,10 @@ define <vscale x 2 x i64> @vp_ctpop_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1475,10 +1475,10 @@ define <vscale x 2 x i64> @vp_ctpop_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1559,10 +1559,10 @@ define <vscale x 4 x i64> @vp_ctpop_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1641,10 +1641,10 @@ define <vscale x 4 x i64> @vp_ctpop_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1725,10 +1725,10 @@ define <vscale x 7 x i64> @vp_ctpop_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1807,10 +1807,10 @@ define <vscale x 7 x i64> @vp_ctpop_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1891,10 +1891,10 @@ define <vscale x 8 x i64> @vp_ctpop_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1973,10 +1973,10 @@ define <vscale x 8 x i64> @vp_ctpop_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2165,10 +2165,10 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a4, a4, -241
; RV64-NEXT: addiw a5, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
; RV64-NEXT: addi a5, a5, 257
; RV64-NEXT: slli a6, a2, 32
; RV64-NEXT: add a2, a2, a6
; RV64-NEXT: slli a6, a3, 32
@ -2356,10 +2356,10 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64_unmasked(<vscale x 16 x i64> %va,
; RV64-NEXT: lui a4, 209715
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 4112
; RV64-NEXT: addiw a3, a3, 1365
; RV64-NEXT: addiw a4, a4, 819
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 257
; RV64-NEXT: addi a3, a3, 1365
; RV64-NEXT: addi a4, a4, 819
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 257
; RV64-NEXT: slli a7, a3, 32
; RV64-NEXT: add a3, a3, a7
; RV64-NEXT: slli a7, a4, 32

64
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
View File

@ -1162,10 +1162,10 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1286,10 +1286,10 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1410,10 +1410,10 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -1534,10 +1534,10 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -2666,10 +2666,10 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -2782,10 +2782,10 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -2898,10 +2898,10 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32
@ -3014,10 +3014,10 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: lui a3, 4112
; RV64I-NEXT: addiw a0, a0, 1365
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: addiw a3, a3, 257
; RV64I-NEXT: addi a0, a0, 1365
; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: addi a2, a2, -241
; RV64I-NEXT: addi a3, a3, 257
; RV64I-NEXT: slli a4, a0, 32
; RV64I-NEXT: add a0, a0, a4
; RV64I-NEXT: slli a4, a1, 32

96
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
View File

@ -1338,10 +1338,10 @@ define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1426,10 +1426,10 @@ define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1516,10 +1516,10 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1604,10 +1604,10 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1694,10 +1694,10 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1782,10 +1782,10 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1872,10 +1872,10 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1960,10 +1960,10 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2050,10 +2050,10 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2138,10 +2138,10 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2334,10 +2334,10 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: srli a6, a1, 3
; RV64-NEXT: sub a7, a0, a1
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a4, a4, -241
; RV64-NEXT: addiw t0, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
; RV64-NEXT: addi t0, a5, 257
; RV64-NEXT: vslidedown.vx v0, v0, a6
; RV64-NEXT: slli a6, a2, 32
; RV64-NEXT: add a6, a2, a6
@ -2537,10 +2537,10 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: sub a6, a0, a1
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a7, a4, -241
; RV64-NEXT: addiw t0, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a7, a4, -241
; RV64-NEXT: addi t0, a5, 257
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32

4
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
View File

@ -797,7 +797,7 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64M-NEXT: vmv.x.s a0, v8
; RV64M-NEXT: lui a1, 349525
; RV64M-NEXT: addiw a1, a1, 1366
; RV64M-NEXT: addi a1, a1, 1366
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srli a1, a0, 63
; RV64M-NEXT: srli a0, a0, 32
@ -825,7 +825,7 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64M-NEXT: vmv.x.s a0, v8
; RV64M-NEXT: lui a1, 349525
; RV64M-NEXT: addiw a1, a1, 1366
; RV64M-NEXT: addi a1, a1, 1366
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srli a1, a0, 63
; RV64M-NEXT: srli a0, a0, 32

80
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
View File

@ -911,9 +911,9 @@ define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %e
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -924,7 +924,7 @@ define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %e
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
; RV64-NEXT: vand.vx v10, v8, a3, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
@ -1048,7 +1048,7 @@ define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v11, v8, a3
; RV64-NEXT: vsrl.vx v12, v8, a5
; RV64-NEXT: vand.vx v12, v12, a0
@ -1069,9 +1069,9 @@ define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -1184,9 +1184,9 @@ define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -1197,7 +1197,7 @@ define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
; RV64-NEXT: vand.vx v12, v8, a3, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
@ -1321,7 +1321,7 @@ define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v10, v8, a3
; RV64-NEXT: vsrl.vx v16, v8, a5
; RV64-NEXT: vand.vx v16, v16, a0
@ -1342,9 +1342,9 @@ define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -1457,9 +1457,9 @@ define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %e
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 209715
; RV64-NEXT: lui a7, 349525
; RV64-NEXT: addiw a5, a5, -241
; RV64-NEXT: addiw a6, a6, 819
; RV64-NEXT: addiw a7, a7, 1365
; RV64-NEXT: addi a5, a5, -241
; RV64-NEXT: addi a6, a6, 819
; RV64-NEXT: addi a7, a7, 1365
; RV64-NEXT: slli t0, a5, 32
; RV64-NEXT: add t0, a5, t0
; RV64-NEXT: slli a5, a6, 32
@ -1470,7 +1470,7 @@ define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %e
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: slli a3, a3, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
; RV64-NEXT: vand.vx v16, v8, a3, v0.t
; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
@ -1594,7 +1594,7 @@ define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v12, v8, a3
; RV64-NEXT: vsrl.vx v24, v8, a5
; RV64-NEXT: vand.vx v24, v24, a0
@ -1615,9 +1615,9 @@ define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl)
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -1787,7 +1787,7 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -1814,9 +1814,9 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -1962,7 +1962,7 @@ define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %ev
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -1986,9 +1986,9 @@ define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %ev
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2166,7 +2166,7 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -2193,9 +2193,9 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3
@ -2341,7 +2341,7 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -2365,9 +2365,9 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: slli a3, a0, 32
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: add a0, a0, a3

16
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
View File

@ -188,7 +188,7 @@ define void @bitreverse_v2i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a3, 16
; RV64-NEXT: lui a4, 4080
; RV64-NEXT: li a5, 255
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: addi a3, a3, -256
; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vsrl.vx v9, v8, a1
; RV64-NEXT: vsrl.vx v10, v8, a2
@ -211,9 +211,9 @@ define void @bitreverse_v2i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a1, 61681
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 349525
; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, 1365
; RV64-NEXT: addi a1, a1, -241
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, 1365
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a1, a1, a4
@ -440,7 +440,7 @@ define void @bitreverse_v4i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a3, 16
; RV64-NEXT: lui a4, 4080
; RV64-NEXT: li a5, 255
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: addi a3, a3, -256
; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vsrl.vx v8, v14, a1
; RV64-NEXT: vsrl.vx v10, v14, a2
@ -463,9 +463,9 @@ define void @bitreverse_v4i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a1, 61681
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 349525
; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, 1365
; RV64-NEXT: addi a1, a1, -241
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, 1365
; RV64-NEXT: slli a4, a1, 32
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a1, a1, a4

20
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
View File

@ -331,7 +331,7 @@ define <2 x i64> @vp_bswap_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
@ -410,7 +410,7 @@ define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 24
; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v11, v8, a3
; RV64-NEXT: vsrl.vx v12, v8, a5
; RV64-NEXT: vand.vx v12, v12, a0
@ -491,7 +491,7 @@ define <4 x i64> @vp_bswap_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
; RV64-NEXT: vand.vx v12, v8, a2, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
@ -570,7 +570,7 @@ define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vsrl.vi v12, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v14, v8, a3
; RV64-NEXT: vsrl.vx v16, v8, a5
; RV64-NEXT: vand.vx v16, v16, a0
@ -651,7 +651,7 @@ define <8 x i64> @vp_bswap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
; RV64-NEXT: vand.vx v16, v8, a2, v0.t
; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
@ -730,7 +730,7 @@ define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vi v16, v8, 8
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v20, v8, a3
; RV64-NEXT: vsrl.vx v24, v8, a5
; RV64-NEXT: vand.vx v24, v24, a0
@ -866,7 +866,7 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -984,7 +984,7 @@ define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0
@ -1131,7 +1131,7 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: slli a2, a2, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
@ -1249,7 +1249,7 @@ define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: addiw a0, a4, -256
; RV64-NEXT: addi a0, a4, -256
; RV64-NEXT: vsrl.vx v16, v8, a3
; RV64-NEXT: vsrl.vx v0, v8, a5
; RV64-NEXT: vand.vx v0, v0, a0

4
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
View File

@ -116,7 +116,7 @@ define void @bswap_v2i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a3, 16
; RV64-NEXT: lui a4, 4080
; RV64-NEXT: li a5, 255
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: addi a3, a3, -256
; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vsrl.vx v9, v8, a1
; RV64-NEXT: vsrl.vx v10, v8, a2
@ -269,7 +269,7 @@ define void @bswap_v4i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a3, 16
; RV64-NEXT: lui a4, 4080
; RV64-NEXT: li a5, 255
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: addi a3, a3, -256
; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: vsrl.vx v12, v8, a2

192
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
View File

@ -931,10 +931,10 @@ define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1035,10 +1035,10 @@ define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1141,10 +1141,10 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1245,10 +1245,10 @@ define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1351,10 +1351,10 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1455,10 +1455,10 @@ define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1561,10 +1561,10 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1665,10 +1665,10 @@ define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1771,10 +1771,10 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -1875,10 +1875,10 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -2101,10 +2101,10 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a6, a4, -241
; RV64-NEXT: addiw a7, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a6, a4, -241
; RV64-NEXT: addi a7, a5, 257
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32
@ -2321,10 +2321,10 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a4, 209715
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 4112
; RV64-NEXT: addiw a7, a3, 1365
; RV64-NEXT: addiw a3, a4, 819
; RV64-NEXT: addiw a4, a5, -241
; RV64-NEXT: addiw a6, a6, 257
; RV64-NEXT: addi a7, a3, 1365
; RV64-NEXT: addi a3, a4, 819
; RV64-NEXT: addi a4, a5, -241
; RV64-NEXT: addi a6, a6, 257
; RV64-NEXT: slli a5, a7, 32
; RV64-NEXT: add a7, a7, a5
; RV64-NEXT: slli a5, a3, 32
@ -3316,10 +3316,10 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3420,10 +3420,10 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3524,10 +3524,10 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3628,10 +3628,10 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3732,10 +3732,10 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3836,10 +3836,10 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -3940,10 +3940,10 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -4044,10 +4044,10 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -4148,10 +4148,10 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -4252,10 +4252,10 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 61681
; RV64-NEXT: lui a3, 4112
; RV64-NEXT: addiw a0, a0, 1365
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addiw a2, a2, -241
; RV64-NEXT: addiw a3, a3, 257
; RV64-NEXT: addi a0, a0, 1365
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: addi a2, a2, -241
; RV64-NEXT: addi a3, a3, 257
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: add a0, a0, a4
; RV64-NEXT: slli a4, a1, 32
@ -4476,10 +4476,10 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a6, a4, -241
; RV64-NEXT: addiw a7, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a6, a4, -241
; RV64-NEXT: addi a7, a5, 257
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32
@ -4696,10 +4696,10 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: lui a4, 209715
; RV64-NEXT: lui a5, 61681
; RV64-NEXT: lui a6, 4112
; RV64-NEXT: addiw a7, a3, 1365
; RV64-NEXT: addiw a3, a4, 819
; RV64-NEXT: addiw a4, a5, -241
; RV64-NEXT: addiw a6, a6, 257
; RV64-NEXT: addi a7, a3, 1365
; RV64-NEXT: addi a3, a4, 819
; RV64-NEXT: addi a4, a5, -241
; RV64-NEXT: addi a6, a6, 257
; RV64-NEXT: slli a5, a7, 32
; RV64-NEXT: add a7, a7, a5
; RV64-NEXT: slli a5, a3, 32

32
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
View File

@ -305,10 +305,10 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -696,10 +696,10 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -1068,10 +1068,10 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -1438,10 +1438,10 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32

96
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
View File

@ -699,10 +699,10 @@ define <2 x i64> @vp_ctpop_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -775,10 +775,10 @@ define <2 x i64> @vp_ctpop_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -853,10 +853,10 @@ define <4 x i64> @vp_ctpop_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -929,10 +929,10 @@ define <4 x i64> @vp_ctpop_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1007,10 +1007,10 @@ define <8 x i64> @vp_ctpop_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1083,10 +1083,10 @@ define <8 x i64> @vp_ctpop_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1161,10 +1161,10 @@ define <15 x i64> @vp_ctpop_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1237,10 +1237,10 @@ define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1315,10 +1315,10 @@ define <16 x i64> @vp_ctpop_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1391,10 +1391,10 @@ define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1577,10 +1577,10 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1708,10 +1708,10 @@ define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a4, a4, -241
; RV64-NEXT: addiw a5, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
; RV64-NEXT: addi a5, a5, 257
; RV64-NEXT: slli a6, a2, 32
; RV64-NEXT: add a2, a2, a6
; RV64-NEXT: slli a6, a3, 32

16
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
View File

@ -173,10 +173,10 @@ define void @ctpop_v2i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -479,10 +479,10 @@ define void @ctpop_v4i64(ptr %x, ptr %y) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32

192
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
View File

@ -774,10 +774,10 @@ define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -856,10 +856,10 @@ define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -940,10 +940,10 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1022,10 +1022,10 @@ define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1106,10 +1106,10 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1188,10 +1188,10 @@ define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1272,10 +1272,10 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1354,10 +1354,10 @@ define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1438,10 +1438,10 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1520,10 +1520,10 @@ define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -1715,10 +1715,10 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a5, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a5, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a3, a1, 32
; RV64-NEXT: add a6, a1, a3
; RV64-NEXT: slli a3, a2, 32
@ -1884,10 +1884,10 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a4, a4, -241
; RV64-NEXT: addiw a5, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
; RV64-NEXT: addi a5, a5, 257
; RV64-NEXT: slli a6, a2, 32
; RV64-NEXT: add a2, a2, a6
; RV64-NEXT: slli a6, a3, 32
@ -2689,10 +2689,10 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2771,10 +2771,10 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2853,10 +2853,10 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -2935,10 +2935,10 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3017,10 +3017,10 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3099,10 +3099,10 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3181,10 +3181,10 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3263,10 +3263,10 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3345,10 +3345,10 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3427,10 +3427,10 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a3, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a3, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a5, a1, 32
; RV64-NEXT: add a1, a1, a5
; RV64-NEXT: slli a5, a2, 32
@ -3620,10 +3620,10 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: lui a2, 209715
; RV64-NEXT: lui a3, 61681
; RV64-NEXT: lui a4, 4112
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addiw a2, a2, 819
; RV64-NEXT: addiw a5, a3, -241
; RV64-NEXT: addiw a4, a4, 257
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: addi a2, a2, 819
; RV64-NEXT: addi a5, a3, -241
; RV64-NEXT: addi a4, a4, 257
; RV64-NEXT: slli a3, a1, 32
; RV64-NEXT: add a6, a1, a3
; RV64-NEXT: slli a3, a2, 32
@ -3789,10 +3789,10 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addiw a2, a2, 1365
; RV64-NEXT: addiw a3, a3, 819
; RV64-NEXT: addiw a4, a4, -241
; RV64-NEXT: addiw a5, a5, 257
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
; RV64-NEXT: addi a5, a5, 257
; RV64-NEXT: slli a6, a2, 32
; RV64-NEXT: add a2, a2, a6
; RV64-NEXT: slli a6, a3, 32

32
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
View File

@ -294,10 +294,10 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -671,10 +671,10 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -1025,10 +1025,10 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32
@ -1373,10 +1373,10 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: lui a4, 4112
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: addiw a2, a2, 819
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: addiw a4, a4, 257
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: addi a3, a3, -241
; RV64I-NEXT: addi a4, a4, 257
; RV64I-NEXT: slli a5, a1, 32
; RV64I-NEXT: add a1, a1, a5
; RV64I-NEXT: slli a5, a2, 32

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