[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

llvm/include/llvm/CodeGen/PeepholeOptimizer.h

@@ -19,8 +19,7 @@ public:
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Passes/PassBuilder.cpp

@@ -448,7 +448,7 @@ public:
     // Intentionally create a virtual register and set NoVRegs property.
     auto &MRI = MF.getRegInfo();
     MRI.createGenericVirtualRegister(LLT::scalar(8));
-    MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+    MF.getProperties().setNoVRegs();
     return PreservedAnalyses::all();
   }
 
@@ -466,19 +466,18 @@ public:
   }
 
   static MachineFunctionProperties getRequiredProperties() {
-    MachineFunctionProperties MFProps;
-    MFProps.set(MachineFunctionProperties::Property::FailedISel);
-    MFProps.set(MachineFunctionProperties::Property::FailsVerification);
-    MFProps.set(MachineFunctionProperties::Property::IsSSA);
-    MFProps.set(MachineFunctionProperties::Property::Legalized);
-    MFProps.set(MachineFunctionProperties::Property::NoPHIs);
-    MFProps.set(MachineFunctionProperties::Property::NoVRegs);
-    MFProps.set(MachineFunctionProperties::Property::RegBankSelected);
-    MFProps.set(MachineFunctionProperties::Property::Selected);
-    MFProps.set(MachineFunctionProperties::Property::TiedOpsRewritten);
-    MFProps.set(MachineFunctionProperties::Property::TracksDebugUserValues);
-    MFProps.set(MachineFunctionProperties::Property::TracksLiveness);
-    return MFProps;
+    return MachineFunctionProperties()
+        .setFailedISel()
+        .setFailsVerification()
+        .setIsSSA()
+        .setLegalized()
+        .setNoPHIs()
+        .setNoVRegs()
+        .setRegBankSelected()
+        .setSelected()
+        .setTiedOpsRewritten()
+        .setTracksDebugUserValues()
+        .setTracksLiveness();
   }
   static StringRef name() { return "RequireAllMachineFunctionPropertiesPass"; }
 };

llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp

@@ -86,8 +86,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

@@ -117,8 +117,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AArch64/AArch64CollectLOH.cpp

@@ -132,8 +132,7 @@ struct AArch64CollectLOH : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }

llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp

@@ -52,8 +52,7 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
   StringRef getPassName() const override {
     return "AArch64 Compress Jump Tables";

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

@@ -188,8 +188,7 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -1121,7 +1121,7 @@ let RecomputePerFunction = 1 in {
   // SelectionDAG's behaviour.
   // FIXME: One day there will probably be a nicer way to check for this, but
   // today is not that day.
-  def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">;
+  def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">;
 }
 
 include "AArch64InstrFormats.td"

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

@@ -233,8 +233,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }

llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp

@@ -173,9 +173,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M,
 
   MachineFunction &MF = MMI->getOrCreateMachineFunction(*F);
   // Remove unnecessary register liveness and set NoVRegs.
-  MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness);
-  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
-  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+  MF.getProperties().resetTracksLiveness().resetIsSSA().setNoVRegs();
   MF.getRegInfo().freezeReservedRegs();
 
   // Create entry block.

llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

@@ -92,8 +92,7 @@ public:
   bool optimizeBlock(MachineBasicBlock *MBB);
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
   StringRef getPassName() const override {
     return "AArch64 Redundant Copy Elimination";

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -544,8 +544,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     // the pipeline since it prevents other infrastructure from reasoning about
     // it's liveness. We use the NoVRegs property instead of IsSSA because
     // IsSSA is removed before VirtRegRewriter runs.
-    if (!MF.getProperties().hasProperty(
-            MachineFunctionProperties::Property::NoVRegs))
+    if (!MF.getProperties().hasNoVRegs())
       markSuperRegs(Reserved, AArch64::LR);
   }
 

llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp

@@ -147,8 +147,7 @@ AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner()
 }
 
 bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

@@ -654,12 +654,9 @@ AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
 }
 
 bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Legalized) &&
-         "Expected a legalized function?");
+  assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
   bool EnableOpt =

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -1257,12 +1257,9 @@ AArch64PostLegalizerLowering::AArch64PostLegalizerLowering()
 }
 
 bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Legalized) &&
-         "Expected a legalized function?");
+  assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
 

llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp

@@ -292,12 +292,9 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
 }
 
 bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Selected) &&
-         "Expected a selected MF");
+  assert(MF.getProperties().hasSelected() && "Expected a selected MF");
 
   bool Changed = false;
   for (auto &BB : MF) {

llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp

@@ -836,8 +836,7 @@ AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
 }
 
 bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

@@ -478,8 +478,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
 }
 
 bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

@@ -253,8 +253,7 @@ AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
 }
 
 bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

@@ -462,8 +462,7 @@ AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
 }
 
 bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp

@@ -58,8 +58,7 @@ public:
   // If there were no phis and we do waterfall expansion machine verifier would
   // fail.
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
@@ -250,8 +249,7 @@ public:
 }
 
 bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // Setup the instruction builder with CSE.

llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp

@@ -53,8 +53,7 @@ public:
   // This pass assigns register banks to all virtual registers, and we maintain
   // this property in subsequent passes
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::RegBankSelected);
+    return MachineFunctionProperties().setRegBankSelected();
   }
 };
 
@@ -199,8 +198,7 @@ static Register getVReg(MachineOperand &Op) {
 }
 
 bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // Setup the instruction builder with CSE.

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

@@ -98,8 +98,7 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/GCNDPPCombine.h

@@ -18,8 +18,7 @@ public:
                         MachineFunctionAnalysisManager &MAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp

@@ -121,8 +121,7 @@ public:
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // FIXME: This pass causes verification failures.
-    MF.getProperties().set(
-        MachineFunctionProperties::Property::FailsVerification);
+    MF.getProperties().setFailsVerification();
 
     TII = MF.getSubtarget<R600Subtarget>().getInstrInfo();
     TRI = &TII->getRegisterInfo();

llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

@@ -111,8 +111,7 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

@@ -618,8 +618,7 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
 
 bool SIFixSGPRCopies::run(MachineFunction &MF) {
   // Only need to run this in SelectionDAG path.
-  if (MF.getProperties().hasProperty(
-        MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return false;
 
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

@@ -191,8 +191,7 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SIFoldOperands.h

@@ -19,8 +19,7 @@ public:
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // namespace llvm

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

@@ -78,8 +78,7 @@ public:
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

@@ -323,8 +323,7 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h

@@ -20,8 +20,7 @@ public:
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

@@ -859,8 +859,7 @@ void Vreg1LoweringHelper::constrainAsLaneMask(Incoming &In) {}
 static bool runFixI1Copies(MachineFunction &MF, MachineDominatorTree &MDT,
                            MachinePostDominatorTree &MPDT) {
   // Only need to run this in SelectionDAG path.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return false;
 
   Vreg1LoweringHelper Helper(&MF, &MDT, &MPDT);

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

@@ -81,9 +81,7 @@ public:
 
   MachineFunctionProperties getClearedProperties() const override {
     // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA)
-        .set(MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setIsSSA().setNoVRegs();
   }
 };
 

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h

@@ -19,9 +19,7 @@ public:
 
   MachineFunctionProperties getClearedProperties() const {
     // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
-    return MachineFunctionProperties()
-        .set(MachineFunctionProperties::Property::IsSSA)
-        .set(MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setIsSSA().setNoVRegs();
   }
 };
 } // namespace llvm

llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp

@@ -166,13 +166,11 @@ public:
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 

llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h

@@ -19,13 +19,11 @@ public:
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 } // namespace llvm

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

@@ -417,8 +417,7 @@ void SIShrinkInstructions::shrinkMadFma(MachineInstr &MI) const {
     return;
 
   // There is no advantage to doing this pre-RA.
-  if (!MF->getProperties().hasProperty(
-          MachineFunctionProperties::Property::NoVRegs))
+  if (!MF->getProperties().hasNoVRegs())
     return;
 
   if (TII->hasAnyModifiersSet(MI))
@@ -951,8 +950,7 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
 
       if (TII->isMIMG(MI.getOpcode()) &&
           ST->getGeneration() >= AMDGPUSubtarget::GFX10 &&
-          MF.getProperties().hasProperty(
-              MachineFunctionProperties::Property::NoVRegs)) {
+          MF.getProperties().hasNoVRegs()) {
         shrinkMIMG(MI);
         continue;
       }
@@ -1063,9 +1061,7 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
       // fold an immediate into the shrunk instruction as a literal operand. In
       // GFX10 VOP3 instructions can take a literal operand anyway, so there is
       // no advantage to doing this.
-      if (ST->hasVOP3Literal() &&
-          !MF.getProperties().hasProperty(
-              MachineFunctionProperties::Property::NoVRegs))
+      if (ST->hasVOP3Literal() && !MF.getProperties().hasNoVRegs())
         continue;
 
       if (ST->hasTrue16BitInsts() && AMDGPU::isTrue16Inst(MI.getOpcode()) &&

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

@@ -256,8 +256,7 @@ public:
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // end anonymous namespace

llvm/lib/Target/AMDGPU/SIWholeQuadMode.h

@@ -18,8 +18,7 @@ public:
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getClearedProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // namespace llvm

llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

@@ -234,8 +234,7 @@ namespace {
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

@@ -51,8 +51,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp

@@ -75,8 +75,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -12157,7 +12157,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                   OpDestReg, OpSizeReg, TotalIterationsReg, IsMemcpy);
 
     // Required to avoid conflict with the MachineVerifier during testing.
-    Properties.reset(MachineFunctionProperties::Property::NoPHIs);
+    Properties.resetNoPHIs();
 
     // Connect the blocks
     TpEntry->addSuccessor(TpLoopBody);

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

@@ -119,8 +119,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; }

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

@@ -489,9 +489,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs).set(
-          MachineFunctionProperties::Property::TracksLiveness);
+      return MachineFunctionProperties().setNoVRegs().setTracksLiveness();
     }
 
     StringRef getPassName() const override {
@@ -1293,7 +1291,7 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
 
   MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
   RDA = &getAnalysis<ReachingDefAnalysis>();
-  MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
+  MF->getProperties().setTracksLiveness();
   MRI = &MF->getRegInfo();
   TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
   TRI = ST.getRegisterInfo();

llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp

@@ -26,8 +26,7 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return "optimise barriers pass"; }

llvm/lib/Target/ARM/MVEVPTBlockPass.cpp

@@ -41,8 +41,7 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

@@ -467,7 +467,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
 
   // In some cases, virtual registers have been introduced, e.g. by uses of
   // emitThumbRegPlusImmInReg.
-  MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
+  MF.getProperties().resetNoVRegs();
 }
 
 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,

llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

@@ -52,8 +52,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/ARM/Thumb2SizeReduction.cpp

@@ -167,8 +167,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp

@@ -218,8 +218,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   void doInitialPlacement(std::vector<MachineInstr *> &CPEMIs);

llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp

@@ -40,8 +40,7 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 

llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

@@ -75,8 +75,7 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp

@@ -38,8 +38,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

@@ -207,8 +207,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
   };
 

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

@@ -73,8 +73,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
   private:

llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp

@@ -80,8 +80,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
   private:

llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp

@@ -70,8 +70,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     static char ID;

llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp

@@ -40,8 +40,7 @@ namespace {
     }
     bool runOnMachineFunction(MachineFunction &Fn) override;
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
   };
 }

llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

@@ -101,8 +101,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
   private:
@@ -198,8 +197,7 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
 
 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
   // FIXME: This pass causes verification failures.
-  MF.getProperties().set(
-      MachineFunctionProperties::Property::FailsVerification);
+  MF.getProperties().setFailsVerification();
 
   auto &HST = MF.getSubtarget<HexagonSubtarget>();
   HII = HST.getInstrInfo();

llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp

@@ -57,8 +57,7 @@ struct Filler : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   void insertDefsUses(MachineBasicBlock::instr_iterator MI,

llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp

@@ -61,8 +61,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

@@ -5729,7 +5729,7 @@ emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB,
     SelectMBBI = Next;
   }
 
-  F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
+  F->getProperties().resetNoPHIs();
   return TailMBB;
 }
 

llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp

@@ -58,8 +58,7 @@ public:
   LoongArchMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

@@ -53,8 +53,7 @@ public:
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/MSP430/MSP430BranchSelector.cpp

@@ -53,8 +53,7 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return "MSP430 Branch Selector"; }

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

@@ -145,8 +145,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/Mips/MipsConstantIslandPass.cpp

@@ -364,8 +364,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &F) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);

llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

@@ -228,8 +228,7 @@ namespace {
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {

llvm/lib/Target/Mips/MipsExpandPseudo.cpp

@@ -41,8 +41,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override {

llvm/lib/Target/Mips/MipsMulMulBugPass.cpp

@@ -40,8 +40,7 @@ public:
   StringRef getPassName() const override { return "Mips VR4300 mulmul bugfix"; }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;

llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp

@@ -122,8 +122,7 @@ MipsPostLegalizerCombiner::MipsPostLegalizerCombiner(bool IsOptNone)
 }
 
 bool MipsPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp

@@ -113,8 +113,7 @@ MipsPreLegalizerCombiner::MipsPreLegalizerCombiner()
     : MachineFunctionPass(ID) {}
 
 bool MipsPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   auto *TPC = &getAnalysis<TargetPassConfig>();

llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

@@ -58,8 +58,7 @@ namespace {
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     StringRef getPassName() const override { return "PowerPC Branch Selector"; }

llvm/lib/Target/PowerPC/PPCCTRLoops.cpp

@@ -253,8 +253,7 @@ void PPCCTRLoops::expandNormalLoops(MachineLoop *ML, MachineInstr *Start,
       MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass
                                          : &PPC::GPRC_and_GPRC_NOR0RegClass);
 
-  Start->getParent()->getParent()->getProperties().reset(
-      MachineFunctionProperties::Property::NoPHIs);
+  Start->getParent()->getParent()->getProperties().resetNoPHIs();
 
   // Generate "PHI" in the header block.
   auto PHIMIB = BuildMI(*ML->getHeader(), ML->getHeader()->getFirstNonPHI(),

llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp

@@ -181,8 +181,7 @@ public:
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

@@ -102,8 +102,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     // This function removes any redundant load immediates. It has two level

llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp

@@ -115,8 +115,7 @@ RISCVO0PreLegalizerCombiner::RISCVO0PreLegalizerCombiner()
 }
 
 bool RISCVO0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp

@@ -123,12 +123,9 @@ RISCVPostLegalizerCombiner::RISCVPostLegalizerCombiner()
 }
 
 bool RISCVPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Legalized) &&
-         "Expected a legalized function?");
+  assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
   bool EnableOpt =

llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp

@@ -121,8 +121,7 @@ RISCVPreLegalizerCombiner::RISCVPreLegalizerCombiner()
 }
 
 bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -21180,7 +21180,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
     SelectMBBI = Next;
   }
 
-  F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
+  F->getProperties().resetNoPHIs();
   return TailMBB;
 }
 

llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp

@@ -48,8 +48,7 @@ struct RISCVLoadStoreOpt : public MachineFunctionPass {
   RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

@@ -47,8 +47,7 @@ public:
   RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {

llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp

@@ -48,8 +48,7 @@ public:
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp

@@ -58,8 +58,7 @@ public:
     // TODO: We could move this closer to regalloc, out of SSA, which would
     // allow scheduling past mask operands. We would need to preserve live
     // intervals.
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -51,8 +51,7 @@ public:
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

@@ -2052,7 +2052,7 @@ static void patchPhis(const Module &M, SPIRVGlobalRegistry *GR,
       }
     }
 
-    MF->getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+    MF->getProperties().setNoPHIs();
   }
 }
 

llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp

@@ -201,8 +201,7 @@ SPIRVPreLegalizerCombiner::SPIRVPreLegalizerCombiner()
 }
 
 bool SPIRVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

@@ -274,8 +274,7 @@ namespace {
 class SPIRVInstructionSelect : public InstructionSelect {
   // We don't use register banks, so unset the requirement for them
   MachineFunctionProperties getRequiredProperties() const override {
-    return InstructionSelect::getRequiredProperties().reset(
-        MachineFunctionProperties::Property::RegBankSelected);
+    return InstructionSelect::getRequiredProperties().resetRegBankSelected();
   }
 };
 } // namespace

llvm/lib/Target/Sparc/DelaySlotFiller.cpp

@@ -58,8 +58,7 @@ namespace {
     }
 
     MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
+      return MachineFunctionProperties().setNoVRegs();
     }
 
     void insertCallDefsUses(MachineBasicBlock::iterator MI,

llvm/lib/Target/SystemZ/SystemZElimCompare.cpp

@@ -71,8 +71,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

@@ -9606,7 +9606,7 @@ static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
     RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
   }
 
-  MF->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
+  MF->getProperties().resetNoPHIs();
 }
 
 MachineBasicBlock *
@@ -10560,7 +10560,7 @@ SystemZTargetLowering::emitMemMemWrapper(MachineInstr &MI,
           MBB->addLiveIn(SystemZ::CC);
       }
     }
-    MF.getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
+    MF.getProperties().resetNoPHIs();
   }
 
   // Handle any remaining bytes with straight-line code.

llvm/lib/Target/SystemZ/SystemZLongBranch.cpp

@@ -140,8 +140,7 @@ public:
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/SystemZ/SystemZShortenInst.cpp

@@ -31,8 +31,7 @@ public:
   bool processBlock(MachineBasicBlock &MBB);
   bool runOnMachineFunction(MachineFunction &F) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp

@@ -50,8 +50,7 @@ class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::TracksLiveness);
+    return MachineFunctionProperties().setTracksLiveness();
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;

llvm/lib/Target/X86/X86CmovConversion.cpp

@@ -872,7 +872,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
   // Reset the NoPHIs property if a PHI was inserted to prevent a conflict with
   // the MachineVerifier during testing.
   if (MIItBegin != MIItEnd)
-    F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
+    F->getProperties().resetNoPHIs();
 
   // Now remove the CMOV(s).
   MBB->erase(MIItBegin, MIItEnd);

llvm/lib/Target/X86/X86CompressEVEX.cpp

@@ -75,8 +75,7 @@ public:
 
   // This pass runs after regalloc and doesn't support VReg operands.
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 };
 

llvm/lib/Target/X86/X86ExpandPseudo.cpp

@@ -51,8 +51,7 @@ public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/X86/X86FastTileConfig.cpp

@@ -62,8 +62,7 @@ public:
   bool runOnMachineFunction(MachineFunction &MFunc) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 
   static char ID;