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Revert "[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo"

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This reverts commit 1a9b55b63a6e18a4692eeb795697cb61ca1b002f.

Causing build bot failures
This commit is contained in:
Craig Topper 2022-03-22 23:41:23 -07:00
parent 1089cdda77
commit 681fd2c11e
2 changed files with 2 additions and 8 deletions
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1
llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
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@ -258,7 +258,6 @@ public:
return;
Register Reg = It->second;
assert(Reg != 0);
if (Reg == 0)
return;

9
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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@ -445,14 +445,9 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
unsigned BitWidth = IntVT.getSizeInBits();
auto It = ValueMap.find(PN);
if (It == ValueMap.end())
Register DestReg = ValueMap[PN];
if (!Register::isVirtualRegister(DestReg))
return;
Register DestReg = It->second;
if (DestReg == 0)
return
assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg");
LiveOutRegInfo.grow(DestReg);
LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];