[RISCV] Check EnsureWholeVectorRegisterMoveValidVTYPE in RISCVInsertVSETVLI::transferBefore. (#190022)
Fixes #189786
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@ -314,7 +314,8 @@ static VSETVLIInfo adjustIncoming(const VSETVLIInfo &PrevInfo,
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// legal for MI, but may not be the state requested by MI.
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void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
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const MachineInstr &MI) const {
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if (RISCV::isVectorCopy(ST->getRegisterInfo(), MI) &&
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if (EnsureWholeVectorRegisterMoveValidVTYPE &&
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RISCV::isVectorCopy(ST->getRegisterInfo(), MI) &&
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(Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) {
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// Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may
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// be coalesced into another vsetvli since we won't demand any fields.
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27
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
Normal file
27
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
Normal file
@ -0,0 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefix=ENABLE
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype=false | FileCheck %s --check-prefix=DISABLE
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define <vscale x 8 x i8> @foo(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2) nounwind {
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; ENABLE-LABEL: foo:
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; ENABLE: # %bb.0: # %entry
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; ENABLE-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; ENABLE-NEXT: vmv1r.v v8, v9
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; ENABLE-NEXT: vmadd.vv v8, v9, v9
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; ENABLE-NEXT: ret
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;
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; DISABLE-LABEL: foo:
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; DISABLE: # %bb.0: # %entry
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; DISABLE-NEXT: vmv1r.v v8, v9
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; DISABLE-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; DISABLE-NEXT: vmadd.vv v8, v9, v9
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; DISABLE-NEXT: ret
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entry:
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%a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
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<vscale x 8 x i8> %1,
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<vscale x 8 x i8> %1,
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<vscale x 8 x i8> %1,
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i64 1, i64 1)
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ret <vscale x 8 x i8> %a
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}
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