[AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (#172057)
On gfx12+, the unified` s_barrier` is lowered to split `s_barrier_signal/s_barrier_wait` pairs. By default, the dependency edge between signal and wait has zero latency, causing the scheduler to emit them adjacent to each other. This misses the opportunity to hide barrier latency. This patch adds synthetic latency to the signal-wait barrier edge to encourage latency hiding. Independent instructions are scheduled in the gap between split barrier signal and wait. The latency is tunable via -amdgpu-barrier-signal-wait-latency. Fixes: SWDEV-567090
This commit is contained in:
Dark Steve
GitHub
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commit
7d381f2a56
@ -6,14 +6,17 @@
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains a DAG scheduling mutation to add latency to
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/// barrier edges between ATOMIC_FENCE instructions and preceding
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/// memory accesses potentially affected by the fence.
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/// This encourages the scheduling of more instructions before
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/// ATOMIC_FENCE instructions. ATOMIC_FENCE instructions may
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/// introduce wait counting or indicate an impending S_BARRIER
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/// wait. Having more instructions in-flight across these
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/// constructs improves latency hiding.
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/// \file This file contains a DAG scheduling mutation to add latency to:
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/// 1. Barrier edges between ATOMIC_FENCE instructions and preceding
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/// memory accesses potentially affected by the fence.
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/// This encourages the scheduling of more instructions before
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/// ATOMIC_FENCE instructions. ATOMIC_FENCE instructions may
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/// introduce wait counting or indicate an impending S_BARRIER
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/// wait. Having more instructions in-flight across these
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/// constructs improves latency hiding.
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/// 2. Barrier edges from S_BARRIER_SIGNAL to S_BARRIER_WAIT.
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/// This encourages independent work to be scheduled between
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/// signal and wait, hiding barrier synchronization latency.
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//
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//===----------------------------------------------------------------------===//
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@ -21,9 +24,16 @@
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<unsigned> BarrierSignalWaitLatencyOpt(
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"amdgpu-barrier-signal-wait-latency",
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cl::desc("Synthetic latency between S_BARRIER_SIGNAL and S_BARRIER_WAIT "
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"to encourage scheduling independent work between them"),
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cl::init(16), cl::Hidden);
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namespace {
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class BarrierLatency : public ScheduleDAGMutation {
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@ -41,38 +51,56 @@ public:
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void apply(ScheduleDAGInstrs *DAG) override;
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};
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void addLatencyToEdge(SDep &PredDep, SUnit &SU, unsigned Latency) {
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SUnit *PredSU = PredDep.getSUnit();
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SDep ForwardD = PredDep;
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ForwardD.setSUnit(&SU);
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for (SDep &SuccDep : PredSU->Succs) {
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if (SuccDep == ForwardD) {
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SuccDep.setLatency(SuccDep.getLatency() + Latency);
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break;
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}
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}
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PredDep.setLatency(PredDep.getLatency() + Latency);
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PredSU->setDepthDirty();
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SU.setDepthDirty();
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}
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void BarrierLatency::apply(ScheduleDAGInstrs *DAG) {
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constexpr unsigned SyntheticLatency = 2000;
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII);
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constexpr unsigned FenceLatency = 2000;
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const unsigned BarrierSignalWaitLatency = BarrierSignalWaitLatencyOpt;
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for (SUnit &SU : DAG->SUnits) {
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const MachineInstr *MI = SU.getInstr();
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if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE)
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continue;
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unsigned Op = MI->getOpcode();
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// Update latency on barrier edges of ATOMIC_FENCE.
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// Ignore scopes not expected to have any latency.
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SyncScope::ID SSID = static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
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if (IgnoredScopes.contains(SSID))
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continue;
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if (Op == AMDGPU::ATOMIC_FENCE) {
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// Update latency on barrier edges of ATOMIC_FENCE.
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// Ignore scopes not expected to have any latency.
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SyncScope::ID SSID =
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static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
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if (IgnoredScopes.contains(SSID))
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continue;
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for (SDep &PredDep : SU.Preds) {
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if (!PredDep.isBarrier())
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continue;
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SUnit *PredSU = PredDep.getSUnit();
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MachineInstr *MI = PredSU->getInstr();
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// Only consider memory loads
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if (!MI->mayLoad() || MI->mayStore())
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continue;
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SDep ForwardD = PredDep;
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ForwardD.setSUnit(&SU);
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for (SDep &SuccDep : PredSU->Succs) {
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if (SuccDep == ForwardD) {
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SuccDep.setLatency(SuccDep.getLatency() + SyntheticLatency);
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break;
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for (SDep &PredDep : SU.Preds) {
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if (!PredDep.isBarrier())
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continue;
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SUnit *PredSU = PredDep.getSUnit();
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MachineInstr *MI = PredSU->getInstr();
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// Only consider memory loads
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if (!MI->mayLoad() || MI->mayStore())
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continue;
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addLatencyToEdge(PredDep, SU, FenceLatency);
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}
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} else if (Op == AMDGPU::S_BARRIER_WAIT) {
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for (SDep &PredDep : SU.Preds) {
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SUnit *PredSU = PredDep.getSUnit();
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const MachineInstr *PredMI = PredSU->getInstr();
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if (TII->isBarrierStart(PredMI->getOpcode())) {
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addLatencyToEdge(PredDep, SU, BarrierSignalWaitLatency);
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}
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}
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PredDep.setLatency(PredDep.getLatency() + SyntheticLatency);
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PredSU->setDepthDirty();
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SU.setDepthDirty();
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}
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}
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}
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197
llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
Normal file
197
llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
Normal file
@ -0,0 +1,197 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-barrier-signal-wait-latency=0 < %s | FileCheck --check-prefix=NOOPT %s
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; Tests for scheduling independent work between s_barrier_signal and s_barrier_wait
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; for latency hiding.
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; Independent work should be scheduled between signal/wait
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define amdgpu_kernel void @test_barrier_independent_valu(ptr addrspace(1) %out, i32 %size) #0 {
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; OPT-LABEL: test_barrier_independent_valu:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b32_e32 v2, 2, v1
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: v_xad_u32 v0, v1, -1, s2
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; OPT-NEXT: global_store_b32 v2, v1, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; OPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v0, v[0:1], off
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v0, s[0:1]
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_independent_valu:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v2, 0x3ff, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b32_e32 v3, 2, v2
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: v_xad_u32 v0, v2, -1, s2
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; NOOPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; NOOPT-NEXT: global_load_b32 v0, v[0:1], off
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v0, s[0:1]
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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store i32 %tid, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx_base = sub i32 %size, 1
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%idx = sub i32 %idx_base, %tid
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%read_addr = getelementptr i32, ptr addrspace(1) %out, i32 %idx
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%val = load i32, ptr addrspace(1) %read_addr
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store i32 %val, ptr addrspace(1) %addr
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ret void
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}
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; No independent work - signal/wait should stay adjacent
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define amdgpu_kernel void @test_barrier_no_independent_work(ptr addrspace(3) %lds) #0 {
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; OPT-LABEL: test_barrier_no_independent_work:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b32 s0, s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshl_add_u32 v1, v0, 2, s0
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; OPT-NEXT: ds_store_b32 v1, v0
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: ds_load_b32 v0, v1
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; OPT-NEXT: s_wait_dscnt 0x0
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; OPT-NEXT: ds_store_b32 v1, v0 offset:4
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_no_independent_work:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b32 s0, s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshl_add_u32 v1, v0, 2, s0
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; NOOPT-NEXT: ds_store_b32 v1, v0
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: ds_load_b32 v0, v1
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; NOOPT-NEXT: s_wait_dscnt 0x0
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; NOOPT-NEXT: ds_store_b32 v1, v0 offset:4
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(3) %lds, i32 %tid
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store i32 %tid, ptr addrspace(3) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%val = load i32, ptr addrspace(3) %addr
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%next = add i32 %tid, 1
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%next_addr = getelementptr i32, ptr addrspace(3) %lds, i32 %next
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store i32 %val, ptr addrspace(3) %next_addr
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ret void
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}
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; Multiple barriers
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define amdgpu_kernel void @test_barrier_multiple(ptr addrspace(1) %out, i32 %size) #0 {
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; OPT-LABEL: test_barrier_multiple:
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; OPT: ; %bb.0: ; %entry
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; OPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; OPT-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b32_e32 v2, 2, v1
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; OPT-NEXT: s_wait_kmcnt 0x0
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; OPT-NEXT: v_xad_u32 v0, v1, -1, s2
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; OPT-NEXT: global_store_b32 v2, v1, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; OPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; OPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; OPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; OPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v3, v[0:1], off
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v3, s[0:1]
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; OPT-NEXT: s_barrier_signal -1
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; OPT-NEXT: s_barrier_wait -1
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; OPT-NEXT: global_load_b32 v0, v[0:1], off offset:-4
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; OPT-NEXT: s_wait_loadcnt 0x0
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; OPT-NEXT: global_store_b32 v2, v0, s[0:1]
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; OPT-NEXT: s_endpgm
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;
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; NOOPT-LABEL: test_barrier_multiple:
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; NOOPT: ; %bb.0: ; %entry
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; NOOPT-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; NOOPT-NEXT: v_and_b32_e32 v2, 0x3ff, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b32_e32 v3, 2, v2
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; NOOPT-NEXT: s_wait_kmcnt 0x0
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; NOOPT-NEXT: v_xad_u32 v0, v2, -1, s2
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; NOOPT-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
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; NOOPT-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
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; NOOPT-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; NOOPT-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
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; NOOPT-NEXT: global_load_b32 v2, v[0:1], off
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v2, s[0:1]
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; NOOPT-NEXT: s_barrier_signal -1
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; NOOPT-NEXT: s_barrier_wait -1
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; NOOPT-NEXT: global_load_b32 v0, v[0:1], off offset:-4
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; NOOPT-NEXT: s_wait_loadcnt 0x0
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; NOOPT-NEXT: global_store_b32 v3, v0, s[0:1]
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; NOOPT-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%addr = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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store i32 %tid, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx1_base = sub i32 %size, 1
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%idx1 = sub i32 %idx1_base, %tid
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%read_addr1 = getelementptr i32, ptr addrspace(1) %out, i32 %idx1
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%val1 = load i32, ptr addrspace(1) %read_addr1
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store i32 %val1, ptr addrspace(1) %addr
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%idx2_base = sub i32 %size, 2
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%idx2 = sub i32 %idx2_base, %tid
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%read_addr2 = getelementptr i32, ptr addrspace(1) %out, i32 %idx2
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%val2 = load i32, ptr addrspace(1) %read_addr2
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store i32 %val2, ptr addrspace(1) %addr
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ret void
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}
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declare void @llvm.amdgcn.s.barrier.signal(i32) #1
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declare void @llvm.amdgcn.s.barrier.wait(i16) #1
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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@ -92,68 +92,68 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 {
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; VARIANT4-LABEL: test_barrier:
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; VARIANT4: ; %bb.0: ; %entry
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; VARIANT4-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
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; VARIANT4-NEXT: v_and_b32_e32 v2, 0x3ff, v0
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; VARIANT4-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; VARIANT4-NEXT: v_lshlrev_b32_e32 v3, 2, v2
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; VARIANT4-NEXT: v_lshlrev_b32_e32 v2, 2, v1
|
||||
; VARIANT4-NEXT: s_wait_kmcnt 0x0
|
||||
; VARIANT4-NEXT: v_xad_u32 v0, v2, -1, s2
|
||||
; VARIANT4-NEXT: global_store_b32 v3, v2, s[0:1]
|
||||
; VARIANT4-NEXT: v_xad_u32 v0, v1, -1, s2
|
||||
; VARIANT4-NEXT: global_store_b32 v2, v1, s[0:1]
|
||||
; VARIANT4-NEXT: s_barrier_signal -1
|
||||
; VARIANT4-NEXT: s_barrier_wait -1
|
||||
; VARIANT4-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
||||
; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; VARIANT4-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
||||
; VARIANT4-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
|
||||
; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; VARIANT4-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
|
||||
; VARIANT4-NEXT: s_barrier_wait -1
|
||||
; VARIANT4-NEXT: global_load_b32 v0, v[0:1], off
|
||||
; VARIANT4-NEXT: s_wait_loadcnt 0x0
|
||||
; VARIANT4-NEXT: global_store_b32 v3, v0, s[0:1]
|
||||
; VARIANT4-NEXT: global_store_b32 v2, v0, s[0:1]
|
||||
; VARIANT4-NEXT: s_endpgm
|
||||
;
|
||||
; VARIANT5-LABEL: test_barrier:
|
||||
; VARIANT5: ; %bb.0: ; %entry
|
||||
; VARIANT5-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
|
||||
; VARIANT5-NEXT: v_and_b32_e32 v2, 0x3ff, v0
|
||||
; VARIANT5-NEXT: v_and_b32_e32 v1, 0x3ff, v0
|
||||
; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; VARIANT5-NEXT: v_lshlrev_b32_e32 v3, 2, v2
|
||||
; VARIANT5-NEXT: v_lshlrev_b32_e32 v2, 2, v1
|
||||
; VARIANT5-NEXT: s_wait_kmcnt 0x0
|
||||
; VARIANT5-NEXT: v_xad_u32 v0, v2, -1, s2
|
||||
; VARIANT5-NEXT: global_store_b32 v3, v2, s[0:1]
|
||||
; VARIANT5-NEXT: v_xad_u32 v0, v1, -1, s2
|
||||
; VARIANT5-NEXT: global_store_b32 v2, v1, s[0:1]
|
||||
; VARIANT5-NEXT: s_barrier_signal -1
|
||||
; VARIANT5-NEXT: s_barrier_wait -1
|
||||
; VARIANT5-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
||||
; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; VARIANT5-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
||||
; VARIANT5-NEXT: v_add_co_u32 v0, vcc_lo, s0, v0
|
||||
; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; VARIANT5-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo
|
||||
; VARIANT5-NEXT: s_barrier_wait -1
|
||||
; VARIANT5-NEXT: global_load_b32 v0, v[0:1], off
|
||||
; VARIANT5-NEXT: s_wait_loadcnt 0x0
|
||||
; VARIANT5-NEXT: global_store_b32 v3, v0, s[0:1]
|
||||
; VARIANT5-NEXT: global_store_b32 v2, v0, s[0:1]
|
||||
; VARIANT5-NEXT: s_endpgm
|
||||
;
|
||||
; VARIANT6-LABEL: test_barrier:
|
||||
; VARIANT6: ; %bb.0: ; %entry
|
||||
; VARIANT6-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
|
||||
; VARIANT6-NEXT: v_and_b32_e32 v1, 0x3ff, v0
|
||||
; VARIANT6-NEXT: s_wait_kmcnt 0x0
|
||||
; VARIANT6-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_and_b32 v4, 0x3ff, v0
|
||||
; VARIANT6-NEXT: s_add_co_i32 s2, s2, -1
|
||||
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; VARIANT6-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_lshlrev_b32 v5, 2, v4
|
||||
; VARIANT6-NEXT: v_sub_nc_u32_e32 v0, s2, v4
|
||||
; VARIANT6-NEXT: global_store_b32 v5, v4, s[0:1]
|
||||
; VARIANT6-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
||||
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
||||
; VARIANT6-NEXT: v_lshlrev_b32_e32 v4, 2, v1
|
||||
; VARIANT6-NEXT: v_sub_nc_u32_e32 v0, s2, v1
|
||||
; VARIANT6-NEXT: global_store_b32 v4, v1, s[0:1]
|
||||
; VARIANT6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
||||
; VARIANT6-NEXT: s_barrier_signal -1
|
||||
; VARIANT6-NEXT: s_barrier_wait -1
|
||||
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; VARIANT6-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
||||
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
||||
; VARIANT6-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
||||
; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
||||
; VARIANT6-NEXT: v_add_co_ci_u32_e64 v1, null, v3, v1, vcc_lo
|
||||
; VARIANT6-NEXT: s_barrier_wait -1
|
||||
; VARIANT6-NEXT: global_load_b32 v0, v[0:1], off
|
||||
; VARIANT6-NEXT: s_wait_loadcnt 0x0
|
||||
; VARIANT6-NEXT: global_store_b32 v5, v0, s[0:1]
|
||||
; VARIANT6-NEXT: global_store_b32 v4, v0, s[0:1]
|
||||
; VARIANT6-NEXT: s_endpgm
|
||||
entry:
|
||||
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
||||
@ -99,8 +99,8 @@ define amdgpu_kernel void @kernel1(ptr addrspace(1) %out, ptr addrspace(3) %in)
|
||||
; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
|
||||
; GFX12-SDAG-NEXT: s_barrier_signal -1
|
||||
; GFX12-SDAG-NEXT: s_barrier_join m0
|
||||
; GFX12-SDAG-NEXT: s_mov_b32 m0, 2
|
||||
; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -1
|
||||
; GFX12-SDAG-NEXT: s_mov_b32 m0, 2
|
||||
; GFX12-SDAG-NEXT: s_barrier_wait 1
|
||||
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-SDAG-NEXT: s_barrier_leave
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user