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AMDGPU/GlobalISel: RegBankLegalize rules for div_fmas/fixup/scale (#188305)

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vangthao95 2026-03-27 10:10:09 -07:00 committed by GitHub
parent f52797c54d
commit 87bec47152
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8 changed files with 481 additions and 348 deletions
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20
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@ -1739,4 +1739,24 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S16, {{Vgpr16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
addRulesForIOpcs({amdgcn_div_fmas}, Standard)
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vcc}})
.Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr64, Vgpr64, Vcc}})
.Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr64, Vgpr64, Vcc}});
addRulesForIOpcs({amdgcn_div_fixup}, Standard)
.Div(S16, {{Vgpr16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}})
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S64, {{Vgpr64}, {IntrId, Vgpr64, Vgpr64, Vgpr64}})
.Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64, Vgpr64, Vgpr64}});
addRulesForIOpcs({amdgcn_div_scale}, Standard)
.Div(S32, {{Vgpr32, Vcc}, {IntrId, Vgpr32, Vgpr32}})
.Uni(S32, {{UniInVgprS32, UniInVcc}, {IntrId, Vgpr32, Vgpr32}})
.Div(S64, {{Vgpr64, Vcc}, {IntrId, Vgpr64, Vgpr64}})
.Uni(S64, {{UniInVgprS64, UniInVcc}, {IntrId, Vgpr64, Vgpr64}});
} // end initialize rules

32
llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
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@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX11 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX11 %s
; Make sure we don't violate the constant bus restriction
@ -120,13 +120,17 @@ define amdgpu_ps float @fcmp_s_s(float inreg %src0, float inreg %src1) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s2, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1.0, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: fcmp_s_s:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: v_cmp_eq_f32_e64 s0, s2, s3
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0
; GFX10PLUS-NEXT: ; return to shader part epilog
%cmp = fcmp oeq float %src0, %src1
%result = select i1 %cmp, float 1.0, float 0.0
@ -156,17 +160,17 @@ define amdgpu_ps float @select_vcc_s_s(float %cmp0, float %cmp1, float inreg %sr
define amdgpu_ps float @select_vcc_fneg_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) {
; GFX9-LABEL: select_vcc_fneg_s_s:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, -v2, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: select_vcc_fneg_s_s:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s2
; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s3
; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s3, -v2, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, -s2, vcc_lo
; GFX10PLUS-NEXT: ; return to shader part epilog
%cmp = fcmp oeq float %cmp0, %cmp1
%neg.src0 = fneg float %src0
@ -199,13 +203,17 @@ define amdgpu_ps float @class_s_s(float inreg %src0, i32 inreg %src1) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1.0, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: class_s_s:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: v_cmp_class_f32_e64 s0, s2, s3
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0
; GFX10PLUS-NEXT: ; return to shader part epilog
%class = call i1 @llvm.amdgcn.class.f32(float %src0, i32 %src1)
%result = select i1 %class, float 1.0, float 0.0

473
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
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File diff suppressed because it is too large Load Diff

8
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
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@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck --check-prefix=GFX7 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
define amdgpu_kernel void @test_div_scale_f32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) {

9
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
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@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
---
name: div_fmas_sss_scc
@ -18,12 +17,12 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s1)
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[AMDGPU_COPY_VCC_SCC]](s1)
; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[INT]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2

3
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
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@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
---
name: div_scale_ss

265
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
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@ -1,15 +1,46 @@
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "load" --filter-out "store" --filter-out "wait" --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
; GCN-LABEL: {{^}}div_fixup_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16(
; VI-SDAG-LABEL: div_fixup_f16:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s11, 0xf000
; VI-SDAG: s_mov_b32 s10, -1
; VI-SDAG: s_mov_b32 s14, s10
; VI-SDAG: s_mov_b32 s15, s11
; VI-SDAG: s_mov_b32 s12, s2
; VI-SDAG: s_mov_b32 s13, s3
; VI-SDAG: s_mov_b32 s16, s4
; VI-SDAG: s_mov_b32 s17, s5
; VI-SDAG: s_mov_b32 s18, s10
; VI-SDAG: s_mov_b32 s19, s11
; VI-SDAG: s_mov_b32 s4, s6
; VI-SDAG: s_mov_b32 s5, s7
; VI-SDAG: s_mov_b32 s6, s10
; VI-SDAG: s_mov_b32 s7, s11
; VI-SDAG: s_mov_b32 s8, s0
; VI-SDAG: s_mov_b32 s9, s1
; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s10, -1
; VI-GISEL: s_mov_b32 s11, 0xf000
; VI-GISEL: s_mov_b64 s[8:9], s[2:3]
; VI-GISEL: s_mov_b64 s[8:9], s[4:5]
; VI-GISEL: s_mov_b64 s[8:9], s[6:7]
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_readfirstlane_b32 s3, v1
; VI-GISEL: v_mov_b32_e32 v0, s3
; VI-GISEL: v_readfirstlane_b32 s4, v2
; VI-GISEL: v_mov_b32_e32 v1, s4
; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v1
; VI-GISEL: s_mov_b64 s[2:3], s[10:11]
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b,
@ -23,14 +54,37 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_a
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; VI: s_movk_i32 s[[A_F16:[0-9]+]], 0x4200{{$}}
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], s[[A_F16]], v[[B_F16]], v[[C_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_a(
; VI-SDAG-LABEL: div_fixup_f16_imm_a:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s14, s6
; VI-SDAG: s_mov_b32 s12, s2
; VI-SDAG: s_mov_b32 s13, s3
; VI-SDAG: s_mov_b32 s15, s7
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, s0, v0, v1
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_a:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_mov_b32_e32 v2, 0x4200
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_readfirstlane_b32 s3, v1
; VI-GISEL: v_mov_b32_e32 v0, s3
; VI-GISEL: v_div_fixup_f16 v0, v2, s2, v0
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 1
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %b,
ptr addrspace(1) %c) {
@ -42,14 +96,37 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_b
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; VI: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}}
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], s[[B_F16]], v[[C_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_b(
; VI-SDAG-LABEL: div_fixup_f16_imm_b:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s14, s6
; VI-SDAG: s_mov_b32 s12, s2
; VI-SDAG: s_mov_b32 s13, s3
; VI-SDAG: s_mov_b32 s15, s7
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, v0, s0, v1
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_b:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_mov_b32_e32 v2, 0x4200
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_readfirstlane_b32 s3, v1
; VI-GISEL: v_mov_b32_e32 v0, s3
; VI-GISEL: v_div_fixup_f16 v0, s2, v2, v0
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 1
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %c) {
@ -61,14 +138,37 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_c
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; VI: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}}
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], s[[C_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_c(
; VI-SDAG-LABEL: div_fixup_f16_imm_c:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s14, s6
; VI-SDAG: s_mov_b32 s12, s2
; VI-SDAG: s_mov_b32 s13, s3
; VI-SDAG: s_mov_b32 s15, s7
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, v0, v1, s0
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_c:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_mov_b32_e32 v2, 0x4200
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_readfirstlane_b32 s3, v1
; VI-GISEL: v_mov_b32_e32 v0, s3
; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v2
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 1
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@ -80,13 +180,32 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_b
; VI-DAG: s_movk_i32 [[AB_F16:s[0-9]+]], 0x4200{{$}}
; GCN-DAG: buffer_load_ushort v[[C_F16:[0-9]+]]
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AB_F16]], [[AB_F16]], v[[C_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b(
; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_b:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s8, s2
; VI-SDAG: s_mov_b32 s9, s3
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, s0, s0, v0
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_b:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: v_mov_b32_e32 v1, 0x4200
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_div_fixup_f16 v0, v1, v1, s2
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 2
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %c) {
entry:
@ -96,13 +215,32 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_b_imm_c
; VI-DAG: s_movk_i32 [[BC_F16:s[0-9]+]], 0x4200{{$}}
; GCN-DAG: buffer_load_ushort v[[A_F16:[0-9]+]]
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], [[BC_F16]], [[BC_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c(
; VI-SDAG-LABEL: div_fixup_f16_imm_b_imm_c:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s8, s2
; VI-SDAG: s_mov_b32 s9, s3
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, v0, s0, s0
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_b_imm_c:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: v_mov_b32_e32 v1, 0x4200
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_div_fixup_f16 v0, s2, v1, v1
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 2
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
@ -112,13 +250,32 @@ entry:
ret void
}
; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_c
; VI-DAG: s_movk_i32 [[AC_F16:s[0-9]+]], 0x4200{{$}}
; GCN-DAG: buffer_load_ushort v[[B_F16:[0-9]+]]
; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AC_F16]], v[[B_F16]], [[AC_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c(
; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_c:
; VI-SDAG: ; %bb.0: ; %entry
; VI-SDAG: s_mov_b32 s7, 0xf000
; VI-SDAG: s_mov_b32 s6, -1
; VI-SDAG: s_mov_b32 s10, s6
; VI-SDAG: s_mov_b32 s11, s7
; VI-SDAG: s_mov_b32 s8, s2
; VI-SDAG: s_mov_b32 s9, s3
; VI-SDAG: s_mov_b32 s4, s0
; VI-SDAG: s_movk_i32 s0, 0x4200
; VI-SDAG: s_mov_b32 s5, s1
; VI-SDAG: v_div_fixup_f16 v0, s0, v0, s0
; VI-SDAG: s_endpgm
;
; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_c:
; VI-GISEL: ; %bb.0: ; %entry
; VI-GISEL: s_mov_b32 s6, -1
; VI-GISEL: s_mov_b32 s7, 0xf000
; VI-GISEL: v_mov_b32_e32 v1, 0x4200
; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
; VI-GISEL: v_readfirstlane_b32 s2, v0
; VI-GISEL: v_div_fixup_f16 v0, v1, s2, v1
; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
; VI-GISEL: s_nop 2
; VI-GISEL: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %b) {
entry:
@ -127,3 +284,17 @@ entry:
store half %r.val, ptr addrspace(1) %r
ret void
}
define half @div_fixup_f16_vgpr(half %a, half %b, half %c) {
; VI-SDAG-LABEL: div_fixup_f16_vgpr:
; VI-SDAG: ; %bb.0:
; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2
; VI-SDAG: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: div_fixup_f16_vgpr:
; VI-GISEL: ; %bb.0:
; VI-GISEL: v_div_fixup_f16 v0, v0, v1, v2
; VI-GISEL: s_setpc_b64 s[30:31]
%r = call half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
ret half %r
}

19
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; RUN: llc -global-isel=0 -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone
declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone
@ -31,3 +32,17 @@ define amdgpu_kernel void @test_div_fixup_f64(ptr addrspace(1) %out, double %a,
store double %result, ptr addrspace(1) %out, align 8
ret void
}
; GCN-LABEL: {{^}}test_div_fixup_f32_vgpr:
; GCN: v_div_fixup_f32
define float @test_div_fixup_f32_vgpr(float %a, float %b, float %c) {
%result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c)
ret float %result
}
; GCN-LABEL: {{^}}test_div_fixup_f64_vgpr:
; GCN: v_div_fixup_f64
define double @test_div_fixup_f64_vgpr(double %a, double %b, double %c) {
%result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c)
ret double %result
}