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AMDGPU/GlobalISel: RegBankLegalize rules for s_memrealtime (#188311)

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vangthao95 2026-03-25 14:35:21 -07:00 committed by GitHub
parent 3692afe4ce
commit 93311617bf
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3 changed files with 10 additions and 5 deletions
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3
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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@ -1463,6 +1463,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{S32}, {{Sgpr32}, {}}})
.Any({{S64}, {{Sgpr64}, {}}});
addRulesForIOpcs({amdgcn_s_memrealtime}, Standard)
.Uni(S64, {{Sgpr64}, {IntrId}});
addRulesForIOpcs({amdgcn_groupstaticsize, amdgcn_pops_exiting_wave_id,
amdgcn_reloc_constant},
Standard)

3
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
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@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s
---
name: memrealtime

9
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
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@ -1,7 +1,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-SDAG %s
; RUN: not llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefix=ERR-GISEL %s
; ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.s.memrealtime
; ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.s.memrealtime
; ERR-GISEL: LLVM ERROR: cannot select: %{{[0-9]+}}:sreg_64(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime)
declare i64 @llvm.amdgcn.s.memrealtime() #0