[SimplfyCFG] Set MD_prof
for select
used for certain conditional simplifications
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parent
628280b597
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961489a611
@ -203,6 +203,8 @@ static cl::opt<unsigned> MaxJumpThreadingLiveBlocks(
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cl::desc("Limit number of blocks a define in a threaded block is allowed "
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"to be live in"));
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extern cl::opt<bool> ProfcheckDisableMetadataFixes;
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STATISTIC(NumBitMaps, "Number of switch instructions turned into bitmaps");
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STATISTIC(NumLinearMaps,
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"Number of switch instructions turned into linear mapping");
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@ -330,6 +332,13 @@ public:
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}
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};
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bool isSelectInRoleOfConjunctionOrDisjunction(const SelectInst *SI) {
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return ((isa<ConstantInt>(SI->getTrueValue()) &&
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(dyn_cast<ConstantInt>(SI->getTrueValue())->isOne())) ||
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(isa<ConstantInt>(SI->getFalseValue()) &&
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(dyn_cast<ConstantInt>(SI->getFalseValue())->isNullValue())));
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}
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} // end anonymous namespace
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/// Return true if all the PHI nodes in the basic block \p BB
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@ -4007,6 +4016,7 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI,
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// Try to update branch weights.
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uint64_t PredTrueWeight, PredFalseWeight, SuccTrueWeight, SuccFalseWeight;
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SmallVector<uint32_t, 2> MDWeights;
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if (extractPredSuccWeights(PBI, BI, PredTrueWeight, PredFalseWeight,
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SuccTrueWeight, SuccFalseWeight)) {
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SmallVector<uint64_t, 8> NewWeights;
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@ -4037,7 +4047,7 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI,
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// Halve the weights if any of them cannot fit in an uint32_t
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fitWeights(NewWeights);
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SmallVector<uint32_t, 8> MDWeights(NewWeights.begin(), NewWeights.end());
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append_range(MDWeights, NewWeights);
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setBranchWeights(PBI, MDWeights[0], MDWeights[1], /*IsExpected=*/false);
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// TODO: If BB is reachable from all paths through PredBlock, then we
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@ -4074,6 +4084,13 @@ static bool performBranchToCommonDestFolding(BranchInst *BI, BranchInst *PBI,
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Value *BICond = VMap[BI->getCondition()];
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PBI->setCondition(
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createLogicalOp(Builder, Opc, PBI->getCondition(), BICond, "or.cond"));
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if (!ProfcheckDisableMetadataFixes)
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if (auto *SI = dyn_cast<SelectInst>(PBI->getCondition()))
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if (!MDWeights.empty()) {
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assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
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setBranchWeights(SI, MDWeights[0], MDWeights[1],
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/*IsExpected=*/false);
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}
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++NumFoldBranchToCommonDest;
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return true;
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@ -4772,6 +4789,14 @@ static bool SimplifyCondBranchToCondBranch(BranchInst *PBI, BranchInst *BI,
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fitWeights(NewWeights);
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setBranchWeights(PBI, NewWeights[0], NewWeights[1], /*IsExpected=*/false);
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// Cond may be a select instruction with the first operand set to "true", or
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// the second to "false" (see how createLogicalOp works for `and` and `or`)
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if (!ProfcheckDisableMetadataFixes)
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if (auto *SI = dyn_cast<SelectInst>(Cond)) {
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assert(isSelectInRoleOfConjunctionOrDisjunction(SI));
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setBranchWeights(SI, NewWeights[0], NewWeights[1],
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/*IsExpected=*/false);
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}
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}
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// OtherDest may have phi nodes. If so, add an entry from PBI's
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@ -1,4 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
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; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s --check-prefixes=NORMAL,BASELINE
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; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -bonus-inst-threshold=2 | FileCheck %s --check-prefixes=NORMAL,AGGRESSIVE
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; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -bonus-inst-threshold=4 | FileCheck %s --check-prefixes=WAYAGGRESSIVE
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@ -11,12 +11,12 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, ptr %input) {
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; BASELINE-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], ptr [[INPUT:%.*]]) {
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; BASELINE-NEXT: [[ENTRY:.*]]:
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; BASELINE-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D]], 3
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; BASELINE-NEXT: br i1 [[CMP]], label %[[COND_END:.*]], label %[[LOR_LHS_FALSE:.*]]
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; BASELINE-NEXT: br i1 [[CMP]], label %[[COND_END:.*]], label %[[LOR_LHS_FALSE:.*]], !prof [[PROF0:![0-9]+]]
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; BASELINE: [[LOR_LHS_FALSE]]:
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; BASELINE-NEXT: [[MUL:%.*]] = shl i32 [[C]], 1
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; BASELINE-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL]], [[A]]
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; BASELINE-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B]]
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; BASELINE-NEXT: br i1 [[CMP1]], label %[[COND_FALSE:.*]], label %[[COND_END]]
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; BASELINE-NEXT: br i1 [[CMP1]], label %[[COND_FALSE:.*]], label %[[COND_END]], !prof [[PROF1:![0-9]+]]
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; BASELINE: [[COND_FALSE]]:
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; BASELINE-NEXT: [[TMP0:%.*]] = load i32, ptr [[INPUT]], align 4
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; BASELINE-NEXT: br label %[[COND_END]]
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@ -31,8 +31,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, ptr %input) {
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; AGGRESSIVE-NEXT: [[MUL:%.*]] = shl i32 [[C]], 1
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; AGGRESSIVE-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL]], [[A]]
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; AGGRESSIVE-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B]]
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; AGGRESSIVE-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false
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; AGGRESSIVE-NEXT: br i1 [[OR_COND]], label %[[COND_FALSE:.*]], label %[[COND_END:.*]]
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; AGGRESSIVE-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false, !prof [[PROF0:![0-9]+]]
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; AGGRESSIVE-NEXT: br i1 [[OR_COND]], label %[[COND_FALSE:.*]], label %[[COND_END:.*]], !prof [[PROF0]]
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; AGGRESSIVE: [[COND_FALSE]]:
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; AGGRESSIVE-NEXT: [[TMP0:%.*]] = load i32, ptr [[INPUT]], align 4
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; AGGRESSIVE-NEXT: br label %[[COND_END]]
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@ -47,8 +47,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, ptr %input) {
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; WAYAGGRESSIVE-NEXT: [[MUL:%.*]] = shl i32 [[C]], 1
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; WAYAGGRESSIVE-NEXT: [[ADD:%.*]] = add nsw i32 [[MUL]], [[A]]
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; WAYAGGRESSIVE-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B]]
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; WAYAGGRESSIVE-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false
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; WAYAGGRESSIVE-NEXT: br i1 [[OR_COND]], label %[[COND_FALSE:.*]], label %[[COND_END:.*]]
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; WAYAGGRESSIVE-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP1]], i1 false, !prof [[PROF0:![0-9]+]]
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; WAYAGGRESSIVE-NEXT: br i1 [[OR_COND]], label %[[COND_FALSE:.*]], label %[[COND_END:.*]], !prof [[PROF0]]
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; WAYAGGRESSIVE: [[COND_FALSE]]:
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; WAYAGGRESSIVE-NEXT: [[TMP0:%.*]] = load i32, ptr [[INPUT]], align 4
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; WAYAGGRESSIVE-NEXT: br label %[[COND_END]]
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@ -58,13 +58,13 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, ptr %input) {
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;
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entry:
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%cmp = icmp sgt i32 %d, 3
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br i1 %cmp, label %cond.end, label %lor.lhs.false
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br i1 %cmp, label %cond.end, label %lor.lhs.false, !prof !0
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lor.lhs.false:
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%mul = shl i32 %c, 1
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%add = add nsw i32 %mul, %a
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%cmp1 = icmp slt i32 %add, %b
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br i1 %cmp1, label %cond.false, label %cond.end
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br i1 %cmp1, label %cond.false, label %cond.end, !prof !1
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cond.false:
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%0 = load i32, ptr %input, align 4
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@ -160,3 +160,14 @@ cond.end:
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%cond = phi i32 [ %0, %cond.false ], [ 0, %lor.lhs.false ],[ 0, %pred_a ],[ 0, %pred_b ]
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ret i32 %cond
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}
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!0 = !{!"branch_weights", i32 7, i32 11}
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!1 = !{!"branch_weights", i32 13, i32 5}
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;.
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; BASELINE: [[PROF0]] = !{!"branch_weights", i32 7, i32 11}
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; BASELINE: [[PROF1]] = !{!"branch_weights", i32 13, i32 5}
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;.
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; AGGRESSIVE: [[PROF0]] = !{!"branch_weights", i32 143, i32 181}
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;.
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; WAYAGGRESSIVE: [[PROF0]] = !{!"branch_weights", i32 143, i32 181}
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;.
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@ -1,12 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
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; RUN: opt < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
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define void @test(ptr %P, ptr %Q, i1 %A, i1 %B) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[B:%.*]], label [[COMMON_RET:%.*]]
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]], !prof [[PROF0:![0-9]+]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[B:%.*]], label [[COMMON_RET:%.*]], !prof [[PROF0]]
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; CHECK: common.ret:
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; CHECK-NEXT: ret void
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; CHECK: b:
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@ -15,9 +15,9 @@ define void @test(ptr %P, ptr %Q, i1 %A, i1 %B) {
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;
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entry:
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br i1 %A, label %a, label %b
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br i1 %A, label %a, label %b, !prof !0
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a:
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br i1 %B, label %b, label %c
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br i1 %B, label %b, label %c, !prof !1
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b:
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store i32 123, ptr %P
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ret void
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@ -146,3 +146,11 @@ Succ:
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}
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declare void @dummy()
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!0 = !{!"branch_weights", i32 3, i32 7}
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!1 = !{!"branch_weights", i32 11, i32 4}
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;.
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; CHECK: attributes #[[ATTR0:[0-9]+]] = { nounwind ssp memory(read) uwtable }
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;.
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; CHECK: [[PROF0]] = !{!"branch_weights", i32 138, i32 12}
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;.
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@ -268,8 +268,8 @@ define void @test7(i1 %a, i1 %b) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6:![0-9]+]]
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]], !prof [[PROF6:![0-9]+]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6]]
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; CHECK: common.ret:
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; CHECK-NEXT: ret void
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; CHECK: Y:
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@ -557,9 +557,9 @@ return:
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define i32 @SimplifyCondBranchToCondBranch(i1 %cmpa, i1 %cmpb) {
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; CHECK-LABEL: @SimplifyCondBranchToCondBranch(
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; CHECK-NEXT: block1:
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA:%.*]], i1 true, i1 [[CMPB:%.*]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA]], i32 0, i32 2, !prof [[PROF13:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF14:![0-9]+]]
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA:%.*]], i1 true, i1 [[CMPB:%.*]], !prof [[PROF13:![0-9]+]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA]], i32 0, i32 2, !prof [[PROF14:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF13]]
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; CHECK-NEXT: ret i32 [[OUTVAL]]
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;
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block1:
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@ -584,9 +584,9 @@ define i32 @SimplifyCondBranchToCondBranchSwap(i1 %cmpa, i1 %cmpb) {
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; CHECK-NEXT: block1:
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; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
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; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF15:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF16:![0-9]+]]
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]], !prof [[PROF15:![0-9]+]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF16:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF15]]
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; CHECK-NEXT: ret i32 [[OUTVAL]]
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;
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block1:
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@ -609,9 +609,9 @@ define i32 @SimplifyCondBranchToCondBranchSwapMissingWeight(i1 %cmpa, i1 %cmpb)
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; CHECK-NEXT: block1:
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; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
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; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF17:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF18:![0-9]+]]
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[CMPA_NOT]], i1 true, i1 [[CMPB_NOT]], !prof [[PROF17:![0-9]+]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof [[PROF18:![0-9]+]]
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; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof [[PROF17]]
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; CHECK-NEXT: ret i32 [[OUTVAL]]
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;
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block1:
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@ -1114,12 +1114,12 @@ exit:
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; CHECK: [[PROF10]] = !{!"branch_weights", i32 8, i32 33}
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; CHECK: [[PROF11]] = !{!"branch_weights", i32 112017436, i32 -735157296}
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; CHECK: [[PROF12]] = !{!"branch_weights", i32 3, i32 5}
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; CHECK: [[PROF13]] = !{!"branch_weights", i32 22, i32 12}
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; CHECK: [[PROF14]] = !{!"branch_weights", i32 34, i32 21}
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; CHECK: [[PROF15]] = !{!"branch_weights", i32 33, i32 14}
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; CHECK: [[PROF16]] = !{!"branch_weights", i32 47, i32 8}
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; CHECK: [[PROF17]] = !{!"branch_weights", i32 6, i32 2}
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; CHECK: [[PROF18]] = !{!"branch_weights", i32 8, i32 2}
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; CHECK: [[PROF13]] = !{!"branch_weights", i32 34, i32 21}
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; CHECK: [[PROF14]] = !{!"branch_weights", i32 22, i32 12}
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; CHECK: [[PROF15]] = !{!"branch_weights", i32 47, i32 8}
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; CHECK: [[PROF16]] = !{!"branch_weights", i32 33, i32 14}
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; CHECK: [[PROF17]] = !{!"branch_weights", i32 8, i32 2}
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; CHECK: [[PROF18]] = !{!"branch_weights", i32 6, i32 2}
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; CHECK: [[PROF19]] = !{!"branch_weights", i32 99, i32 1}
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; CHECK: [[PROF20]] = !{!"branch_weights", i32 1, i32 99}
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; CHECK: [[PROF21]] = !{!"branch_weights", i32 199, i32 1}
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