Revert "AMDGPU: Fold frame indexes into disjoint s_or_b32" (#189074)
Reverts llvm/llvm-project#102345 unblock bot: https://lab.llvm.org/buildbot/#/builders/10/builds/25403
This commit is contained in:
Kewen Meng
GitHub
parent
88bc265295
commit
a996f2a8db
@ -2807,12 +2807,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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return true;
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}
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case AMDGPU::S_ADD_I32:
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case AMDGPU::S_ADD_U32:
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case AMDGPU::S_OR_B32: {
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if (MI->getOpcode() == AMDGPU::S_OR_B32 &&
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!MI->getFlag(MachineInstr::Disjoint))
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break;
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case AMDGPU::S_ADD_U32: {
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// TODO: Handle s_or_b32, s_and_b32.
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unsigned OtherOpIdx = FIOperandNum == 1 ? 2 : 1;
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MachineOperand &OtherOp = MI->getOperand(OtherOpIdx);
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@ -174,167 +174,6 @@ body: |
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...
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---
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name: s_or_b32_disjoint__inline_imm__fi_offset0
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 32, alignment: 16 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; MUBUFW64-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
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; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr4, implicit-def $scc
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; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; MUBUFW32-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
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; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr4, implicit-def $scc
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; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW64-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
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; FLATSCRW64: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr32, implicit-def $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW32-LABEL: name: s_or_b32_disjoint__inline_imm__fi_offset0
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; FLATSCRW32: renamable $sgpr7 = disjoint S_OR_B32 12, $sgpr32, implicit-def $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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renamable $sgpr7 = disjoint S_OR_B32 12, %stack.0, implicit-def $scc
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SI_RETURN implicit $sgpr7, implicit $scc
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...
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---
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name: s_or_b32_disjoint__literal__fi_offset96
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 96, alignment: 16 }
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- { id: 1, size: 24, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; MUBUFW64-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
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; MUBUFW64: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr4, implicit-def $scc
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; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; MUBUFW32-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
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; MUBUFW32: renamable $sgpr4 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr4, implicit-def $scc
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; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW64-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
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; FLATSCRW64: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr32, implicit-def $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW32-LABEL: name: s_or_b32_disjoint__literal__fi_offset96
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; FLATSCRW32: renamable $sgpr7 = disjoint S_OR_B32 164, $sgpr32, implicit-def $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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renamable $sgpr7 = disjoint S_OR_B32 68, %stack.1, implicit-def $scc
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SI_RETURN implicit $sgpr7, implicit $scc
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...
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---
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name: s_or_b32_disjoint__sgpr__fi_literal_offset
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 80, alignment: 16 }
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- { id: 1, size: 48, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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liveins: $sgpr8
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; MUBUFW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
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; MUBUFW64: liveins: $sgpr8
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; MUBUFW64-NEXT: {{ $}}
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; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
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; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; MUBUFW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
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; MUBUFW32: liveins: $sgpr8
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; MUBUFW32-NEXT: {{ $}}
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; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
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; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
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; FLATSCRW64: liveins: $sgpr8
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; FLATSCRW64-NEXT: {{ $}}
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; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
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; FLATSCRW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_literal_offset
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; FLATSCRW32: liveins: $sgpr8
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; FLATSCRW32-NEXT: {{ $}}
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; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
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; FLATSCRW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 80, implicit-def $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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renamable $sgpr7 = disjoint S_OR_B32 $sgpr8, %stack.1, implicit-def $scc
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SI_RETURN implicit $sgpr7, implicit $scc
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...
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---
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name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 32, alignment: 16 }
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- { id: 1, size: 48, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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liveins: $sgpr8
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; MUBUFW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
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; MUBUFW64: liveins: $sgpr8
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; MUBUFW64-NEXT: {{ $}}
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; MUBUFW64-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
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; MUBUFW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
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; MUBUFW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; MUBUFW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
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; MUBUFW32: liveins: $sgpr8
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; MUBUFW32-NEXT: {{ $}}
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; MUBUFW32-NEXT: renamable $sgpr7 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr7, $sgpr8, implicit-def $scc
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; MUBUFW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
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; MUBUFW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW64-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
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; FLATSCRW64: liveins: $sgpr8
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; FLATSCRW64-NEXT: {{ $}}
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; FLATSCRW64-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
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; FLATSCRW64-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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;
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; FLATSCRW32-LABEL: name: s_or_b32_disjoint__sgpr__fi_inlineimm_offset
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; FLATSCRW32: liveins: $sgpr8
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; FLATSCRW32-NEXT: {{ $}}
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; FLATSCRW32-NEXT: renamable $sgpr7 = S_OR_B32 killed $sgpr32, $sgpr8, implicit-def $scc
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; FLATSCRW32-NEXT: renamable $sgpr7 = disjoint S_OR_B32 killed renamable $sgpr7, 32, implicit-def $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr7, implicit $scc
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renamable $sgpr7 = disjoint S_OR_B32 $sgpr8, %stack.1, implicit-def $scc
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SI_RETURN implicit $sgpr7, implicit $scc
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...
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---
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name: s_and_b32__sgpr__fi_literal_offset
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tracksRegLiveness: true
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@ -1,220 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX940 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
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define void @s_add_use_fi_sgpr_offset(i32 inreg %soffset) #0 {
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; GFX7-LABEL: s_add_use_fi_sgpr_offset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b32 s7, s33
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; GFX7-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX7-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX7-NEXT: s_mov_b32 s8, s34
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; GFX7-NEXT: s_mov_b32 s34, s32
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; GFX7-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX7-NEXT: s_and_b32 s4, s16, 31
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; GFX7-NEXT: s_lshr_b32 s5, s33, 6
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; GFX7-NEXT: s_addk_i32 s5, 0x120
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; GFX7-NEXT: s_lshr_b32 s6, s33, 6
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; GFX7-NEXT: s_add_i32 s6, s6, 16
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; GFX7-NEXT: ;;#ASMSTART
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; GFX7-NEXT: ; use s5
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; GFX7-NEXT: ;;#ASMEND
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; GFX7-NEXT: s_lshr_b32 s5, s33, 6
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; GFX7-NEXT: s_or_b32 s4, s5, s4
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; GFX7-NEXT: s_addk_i32 s4, 0x120
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; GFX7-NEXT: ;;#ASMSTART
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; GFX7-NEXT: ; use s4
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; GFX7-NEXT: ;;#ASMEND
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; GFX7-NEXT: s_mov_b32 s32, s34
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; GFX7-NEXT: s_mov_b32 s34, s8
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; GFX7-NEXT: s_mov_b32 s33, s7
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: s_add_use_fi_sgpr_offset:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: s_mov_b32 s7, s33
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; GFX8-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX8-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX8-NEXT: s_mov_b32 s8, s34
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; GFX8-NEXT: s_mov_b32 s34, s32
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; GFX8-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX8-NEXT: s_and_b32 s4, s16, 31
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; GFX8-NEXT: s_lshr_b32 s5, s33, 6
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; GFX8-NEXT: s_addk_i32 s5, 0x120
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; GFX8-NEXT: s_lshr_b32 s6, s33, 6
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; GFX8-NEXT: s_add_i32 s6, s6, 16
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; GFX8-NEXT: ;;#ASMSTART
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; GFX8-NEXT: ; use s5
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; GFX8-NEXT: ;;#ASMEND
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; GFX8-NEXT: s_lshr_b32 s5, s33, 6
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; GFX8-NEXT: s_or_b32 s4, s5, s4
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; GFX8-NEXT: s_addk_i32 s4, 0x120
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; GFX8-NEXT: ;;#ASMSTART
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; GFX8-NEXT: ; use s4
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; GFX8-NEXT: ;;#ASMEND
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; GFX8-NEXT: s_mov_b32 s32, s34
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; GFX8-NEXT: s_mov_b32 s34, s8
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; GFX8-NEXT: s_mov_b32 s33, s7
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX900-LABEL: s_add_use_fi_sgpr_offset:
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; GFX900: ; %bb.0:
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; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX900-NEXT: s_mov_b32 s7, s33
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; GFX900-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX900-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX900-NEXT: s_mov_b32 s8, s34
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; GFX900-NEXT: s_mov_b32 s34, s32
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; GFX900-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX900-NEXT: s_and_b32 s4, s16, 31
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; GFX900-NEXT: s_lshr_b32 s5, s33, 6
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; GFX900-NEXT: s_addk_i32 s5, 0x120
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; GFX900-NEXT: s_lshr_b32 s6, s33, 6
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; GFX900-NEXT: s_add_i32 s6, s6, 16
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; GFX900-NEXT: ;;#ASMSTART
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; GFX900-NEXT: ; use s5
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; GFX900-NEXT: ;;#ASMEND
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; GFX900-NEXT: s_lshr_b32 s5, s33, 6
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; GFX900-NEXT: s_or_b32 s4, s5, s4
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; GFX900-NEXT: s_addk_i32 s4, 0x120
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; GFX900-NEXT: ;;#ASMSTART
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; GFX900-NEXT: ; use s4
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; GFX900-NEXT: ;;#ASMEND
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; GFX900-NEXT: s_mov_b32 s32, s34
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; GFX900-NEXT: s_mov_b32 s34, s8
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; GFX900-NEXT: s_mov_b32 s33, s7
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; GFX900-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: s_add_use_fi_sgpr_offset:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s7, s33
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; GFX10-NEXT: s_add_i32 s33, s32, 0x3e0
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; GFX10-NEXT: s_mov_b32 s8, s34
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; GFX10-NEXT: s_and_b32 s33, s33, 0xfffffc00
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; GFX10-NEXT: s_mov_b32 s34, s32
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; GFX10-NEXT: s_add_i32 s32, s32, 0x22800
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; GFX10-NEXT: s_and_b32 s4, s16, 31
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; GFX10-NEXT: s_lshr_b32 s5, s33, 5
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; GFX10-NEXT: s_mov_b32 s32, s34
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; GFX10-NEXT: s_addk_i32 s5, 0x120
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; GFX10-NEXT: s_lshr_b32 s6, s33, 5
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; GFX10-NEXT: s_mov_b32 s34, s8
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; GFX10-NEXT: s_add_i32 s6, s6, 16
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; GFX10-NEXT: s_lshr_b32 s9, s33, 5
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s5
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: s_or_b32 s4, s9, s4
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; GFX10-NEXT: s_mov_b32 s33, s7
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; GFX10-NEXT: s_addk_i32 s4, 0x120
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s4
|
||||
; GFX10-NEXT: ;;#ASMEND
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX940-LABEL: s_add_use_fi_sgpr_offset:
|
||||
; GFX940: ; %bb.0:
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX940-NEXT: s_mov_b32 s3, s33
|
||||
; GFX940-NEXT: s_add_i32 s33, s32, 31
|
||||
; GFX940-NEXT: s_andn2_b32 s33, s33, 31
|
||||
; GFX940-NEXT: s_mov_b32 s4, s34
|
||||
; GFX940-NEXT: s_mov_b32 s34, s32
|
||||
; GFX940-NEXT: s_addk_i32 s32, 0x1140
|
||||
; GFX940-NEXT: s_and_b32 s0, s0, 31
|
||||
; GFX940-NEXT: s_add_i32 s2, s33, 0x120
|
||||
; GFX940-NEXT: s_mov_b32 s1, s2
|
||||
; GFX940-NEXT: s_add_i32 s5, s33, 16
|
||||
; GFX940-NEXT: s_mov_b32 s2, s5
|
||||
; GFX940-NEXT: ;;#ASMSTART
|
||||
; GFX940-NEXT: ; use s1
|
||||
; GFX940-NEXT: ;;#ASMEND
|
||||
; GFX940-NEXT: s_or_b32 s1, s33, s0
|
||||
; GFX940-NEXT: s_or_b32 s0, s1, 0x120
|
||||
; GFX940-NEXT: ;;#ASMSTART
|
||||
; GFX940-NEXT: ; use s0
|
||||
; GFX940-NEXT: ;;#ASMEND
|
||||
; GFX940-NEXT: s_mov_b32 s32, s34
|
||||
; GFX940-NEXT: s_mov_b32 s34, s4
|
||||
; GFX940-NEXT: s_mov_b32 s33, s3
|
||||
; GFX940-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-LABEL: s_add_use_fi_sgpr_offset:
|
||||
; GFX11: ; %bb.0:
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX11-NEXT: s_mov_b32 s3, s33
|
||||
; GFX11-NEXT: s_add_i32 s33, s32, 31
|
||||
; GFX11-NEXT: s_mov_b32 s4, s34
|
||||
; GFX11-NEXT: s_and_not1_b32 s33, s33, 31
|
||||
; GFX11-NEXT: s_mov_b32 s34, s32
|
||||
; GFX11-NEXT: s_addk_i32 s32, 0x1140
|
||||
; GFX11-NEXT: s_and_b32 s0, s0, 31
|
||||
; GFX11-NEXT: s_add_i32 s2, s33, 0x120
|
||||
; GFX11-NEXT: s_add_i32 s5, s33, 16
|
||||
; GFX11-NEXT: s_mov_b32 s1, s2
|
||||
; GFX11-NEXT: s_mov_b32 s2, s5
|
||||
; GFX11-NEXT: s_or_b32 s5, s33, s0
|
||||
; GFX11-NEXT: ;;#ASMSTART
|
||||
; GFX11-NEXT: ; use s1
|
||||
; GFX11-NEXT: ;;#ASMEND
|
||||
; GFX11-NEXT: s_or_b32 s0, s5, 0x120
|
||||
; GFX11-NEXT: ;;#ASMSTART
|
||||
; GFX11-NEXT: ; use s0
|
||||
; GFX11-NEXT: ;;#ASMEND
|
||||
; GFX11-NEXT: s_mov_b32 s32, s34
|
||||
; GFX11-NEXT: s_mov_b32 s34, s4
|
||||
; GFX11-NEXT: s_mov_b32 s33, s3
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-LABEL: s_add_use_fi_sgpr_offset:
|
||||
; GFX12: ; %bb.0:
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: s_mov_b32 s3, s33
|
||||
; GFX12-NEXT: s_add_co_i32 s33, s32, 31
|
||||
; GFX12-NEXT: s_mov_b32 s4, s34
|
||||
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
|
||||
; GFX12-NEXT: s_and_not1_b32 s33, s33, 31
|
||||
; GFX12-NEXT: s_mov_b32 s34, s32
|
||||
; GFX12-NEXT: s_addk_co_i32 s32, 0x1140
|
||||
; GFX12-NEXT: s_and_b32 s0, s0, 31
|
||||
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
|
||||
; GFX12-NEXT: s_add_co_i32 s2, s33, 0x100
|
||||
; GFX12-NEXT: s_or_b32 s5, s33, s0
|
||||
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
|
||||
; GFX12-NEXT: s_mov_b32 s1, s2
|
||||
; GFX12-NEXT: s_mov_b32 s2, s33
|
||||
; GFX12-NEXT: s_or_b32 s0, s5, 0x100
|
||||
; GFX12-NEXT: ;;#ASMSTART
|
||||
; GFX12-NEXT: ; use s1
|
||||
; GFX12-NEXT: ;;#ASMEND
|
||||
; GFX12-NEXT: ;;#ASMSTART
|
||||
; GFX12-NEXT: ; use s0
|
||||
; GFX12-NEXT: ;;#ASMEND
|
||||
; GFX12-NEXT: s_mov_b32 s32, s34
|
||||
; GFX12-NEXT: s_mov_b32 s34, s4
|
||||
; GFX12-NEXT: s_mov_b32 s33, s3
|
||||
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
%filler = alloca [256 x i8], align 16, addrspace(5)
|
||||
%alloca = alloca [4096 x i8], align 32, addrspace(5)
|
||||
|
||||
%soffset.and = and i32 %soffset, 31
|
||||
|
||||
call void asm sideeffect "; use $0", "s,s"(ptr addrspace(5) %alloca, ptr addrspace(5) %filler)
|
||||
%gep = getelementptr inbounds nuw [4096 x i8], ptr addrspace(5) %alloca, i32 0, i32 %soffset.and
|
||||
call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %gep)
|
||||
ret void
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user