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[llvm] Remove unused local variables (NFC) (#138467)

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This commit is contained in:
Kazu Hirata 2025-05-04 13:05:18 -07:00 committed by GitHub
parent 142f99ad64
commit c51a3aa6ce
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GPG Key ID: B5690EEEBB952194
16 changed files with 0 additions and 33 deletions
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1
llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
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@ -523,7 +523,6 @@ static void computeFunctionSummary(
auto *MemProfMD = I.getMetadata(LLVMContext::MD_memprof);
if (MemProfMD) {
std::vector<MIBInfo> MIBs;
std::vector<uint64_t> TotalSizes;
std::vector<std::vector<ContextTotalSize>> ContextSizeInfos;
for (auto &MDOp : MemProfMD->operands()) {
auto *MIBMD = cast<const MDNode>(MDOp);

5
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -15197,10 +15197,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
if (ISD::isExtVecInRegOpcode(N0.getOpcode())) {
SDValue N00 = N0.getOperand(0);
unsigned N00Bits = N00.getScalarValueSizeInBits();
unsigned DstElts = N0.getValueType().getVectorMinNumElements();
unsigned SrcElts = N00.getValueType().getVectorMinNumElements();
bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts);
if ((N00Bits == ExtVTBits ||
(!IsZext && (N00Bits < ExtVTBits ||
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) &&
@ -20772,8 +20769,6 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
// We're checking for cases where we have common "c3 * A" expressions.
bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode,
SDValue ConstNode) {
APInt Val;
// If the add only has one use, and the target thinks the folding is
// profitable or does not lead to worse code, this would be OK to do.
if (AddNode->hasOneUse() &&

1
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -7965,7 +7965,6 @@ bool TargetLowering::expandDIVREMByConstant(SDNode *N,
// If we shifted the input, shift the remainder left and add the bits we
// shifted off the input.
if (TrailingZeros) {
APInt Mask = APInt::getLowBitsSet(HBitWidth, TrailingZeros);
RemL = DAG.getNode(ISD::SHL, dl, HiLoVT, RemL,
DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
RemL = DAG.getNode(ISD::ADD, dl, HiLoVT, RemL, PartialRem);

4
llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
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@ -454,10 +454,6 @@ unsigned DWARFVerifier::verifyUnitSection(const DWARFSection &S) {
bool hasDIE = DebugInfoData.isValidOffset(Offset);
DWARFUnitVector TypeUnitVector;
DWARFUnitVector CompileUnitVector;
/// A map that tracks all references (converted absolute references) so we
/// can verify each reference points to a valid DIE and not an offset that
/// lies between to valid DIEs.
ReferenceMap CrossUnitReferences;
while (hasDIE) {
if (!verifyUnitHeader(DebugInfoData, &Offset, UnitIdx, UnitType,
isUnitDWARF64)) {

1
llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
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@ -191,7 +191,6 @@ Error SimpleRemoteEPCServer::sendSetupMessage(
using namespace SimpleRemoteEPCDefaultBootstrapSymbolNames;
std::vector<char> SetupPacket;
SimpleRemoteEPCExecutorInfo EI;
EI.TargetTriple = sys::getProcessTriple();
if (auto PageSize = sys::Process::getPageSize())

1
llvm/lib/ObjCopy/wasm/WasmReader.cpp
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@ -19,7 +19,6 @@ Expected<std::unique_ptr<Object>> Reader::create() const {
auto Obj = std::make_unique<Object>();
Obj->Header = WasmObj.getHeader();
Obj->isRelocatableObject = WasmObj.isRelocatableObject();
std::vector<Section> Sections;
Obj->Sections.reserve(WasmObj.getNumSections());
for (const SectionRef &Sec : WasmObj.sections()) {
const WasmSection &WS = WasmObj.getWasmSection(Sec);

2
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
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@ -841,8 +841,6 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
std::vector<unsigned> I1Defs;
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
BI != BE; ++BI) {

2
llvm/lib/Target/ARM/ARMSubtarget.cpp
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@ -489,8 +489,6 @@ ARMSubtarget::PushPopSplitVariation
ARMSubtarget::getPushPopSplitVariation(const MachineFunction &MF) const {
const Function &F = MF.getFunction();
const MachineFrameInfo &MFI = MF.getFrameInfo();
const std::vector<CalleeSavedInfo> CSI =
MF.getFrameInfo().getCalleeSavedInfo();
// Thumb1 always splits the pushes at R7, because the Thumb1 push instruction
// cannot use high registers except for lr.

6
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
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@ -1323,12 +1323,6 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End,
// Select the definition points, and generate the assignment between
// these points and the uses.
// For each candidate offset, keep a pair CandData consisting of
// the total number of ranges containing that candidate, and the
// vector of corresponding RangeTree nodes.
using CandData = std::pair<unsigned, SmallVector<RangeTree::Node*,8>>;
std::map<int32_t, CandData> CandMap;
RangeTree Tree;
for (const OffsetRange &R : Ranges)
Tree.add(R);

1
llvm/lib/Transforms/IPO/IROutliner.cpp
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@ -2296,7 +2296,6 @@ void IROutliner::deduplicateExtractedSections(
fillOverallFunction(M, CurrentGroup, OutputStoreBBs, FuncsToRemove,
OutputMappings);
std::vector<Value *> SortedKeys;
for (unsigned Idx = 1; Idx < CurrentGroup.Regions.size(); Idx++) {
CurrentOS = CurrentGroup.Regions[Idx];
AttributeFuncs::mergeAttributesForOutlining(*CurrentGroup.OutlinedFunction,

1
llvm/tools/sancov/sancov.cpp
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@ -1003,7 +1003,6 @@ static void printNotCoveredFunctions(const SymbolizedCoverage &CovData,
// Read list of files and merges their coverage info.
static void readAndPrintRawCoverage(const std::vector<std::string> &FileNames,
raw_ostream &OS) {
std::vector<std::unique_ptr<RawCoverage>> Covs;
for (const auto &FileName : FileNames) {
auto Cov = RawCoverage::read(FileName);
if (!Cov)

1
llvm/unittests/DebugInfo/CodeView/TypeHashingTest.cpp
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@ -97,7 +97,6 @@ TEST(TypeHashingTest, ContentHash) {
// LF_PROCEDURE 0x1004 {int** func(char**, int***)}
// ArgList = 0x1003
// ReturnType = 0x1001
std::vector<GloballyHashedType> Ordering1Hashes;
CharPP[0] = createPointerRecord(Ordering1, CharP);
IntPP[0] = createPointerRecord(Ordering1, IntP);
IntPPP[0] = createPointerRecord(Ordering1, IntPP[0]);

2
llvm/unittests/XRay/GraphTest.cpp
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@ -85,8 +85,6 @@ template <typename T> void graphVertexTester(T &G) {
}
template <typename T> void graphEdgeTester(T &G) {
std::set<unsigned> V({1u, 2u, 3u, 4u, 5u, 6u});
std::set<std::pair<unsigned, unsigned>> E(
{{1u, 2u}, {2u, 3u}, {6u, 3u}, {4u, 6u}, {2u, 4u}, {2u, 5u}, {4u, 5u}});
std::vector<unsigned> VA({0u, 3u, 5u, 7u, 11u, 13u, 17u});

3
llvm/utils/TableGen/AsmWriterEmitter.cpp
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@ -869,9 +869,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
DenseMap<const Record *, unsigned> MCOpPredicateMap;
for (auto &Aliases : AliasMap) {
// Collection of instruction alias rules. May contain ambiguous rules.
std::vector<IAPrinter> IAPs;
for (auto &Alias : Aliases.second) {
const CodeGenInstAlias &CGA = Alias.first;
unsigned LastOpNo = CGA.ResultInstOperandIndex.size();

1
llvm/utils/TableGen/DFAEmitter.cpp
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@ -118,7 +118,6 @@ void DfaEmitter::emit(StringRef Name, raw_ostream &OS) {
OS << "// to by index in " << Name << "Transitions[].\n";
SequenceToOffsetTable<DfaTransitionInfo> Table;
std::map<DfaTransitionInfo, unsigned> EmittedIndices;
for (auto &T : DfaTransitions)
Table.add(T.second.second);
Table.layout();

1
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
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@ -567,7 +567,6 @@ void CombineRuleOperandTypeChecker::getInstEqClasses(
CombineRuleOperandTypeChecker::TypeEquivalenceClasses
CombineRuleOperandTypeChecker::getRuleEqClasses() const {
StringMap<unsigned> OpNameToEqClassIdx;
TypeEquivalenceClasses TECs;
if (DebugTypeInfer)