NFC: Use -LABEL more
There were a number of tests needing updates for D91734, and I added a bunch of LABEL directives to help track down where those had to go. These directives are an improvement independent of the functional patch, so I'm committing them as their own separate patch.
This commit is contained in:
Paul Robinson
parent
31732e6f52
commit
e5eb5c8a7f
@ -78,7 +78,7 @@ declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8
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; Test materialization of integers. Target-independent selector handles this.
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define i32 @t2() {
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entry:
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; CHECK-LABEL: t2
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; CHECK-LABEL: t2:
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; CHECK: mov x0, xzr
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; CHECK: mov w1, #-8
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; CHECK: mov [[REG2:w[0-9]+]], #1023
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@ -99,6 +99,7 @@ declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext
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declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 %bp15, i8 %bp17, i8 %bp18, i8 %bp19)
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define void @caller_b1f() {
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entry:
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; CHECK-LABEL: caller_b1f
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; CHECK-BE-LABEL: caller_b1f
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; CHECK-BE: strb w{{.*}}, [sp, #7]
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call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42)
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@ -2,7 +2,7 @@
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define void @t0(i32 %a) nounwind {
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entry:
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; CHECK: t0
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; CHECK-LABEL: t0:
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; CHECK: str {{w[0-9]+}}, [sp, #12]
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; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
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; CHECK-NEXT: str [[REGISTER]], [sp, #12]
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@ -15,7 +15,7 @@ entry:
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}
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define void @t1(i64 %a) nounwind {
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; CHECK: t1
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; CHECK-LABEL: t1:
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; CHECK: str {{x[0-9]+}}, [sp, #8]
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; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
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; CHECK-NEXT: str [[REGISTER]], [sp, #8]
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@ -29,7 +29,7 @@ define void @t1(i64 %a) nounwind {
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define zeroext i1 @i1(i1 %a) nounwind {
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entry:
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; CHECK: @i1
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; CHECK-LABEL: i1:
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK: strb [[REG]], [sp, #15]
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; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15]
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@ -84,7 +84,7 @@ entry:
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}
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define void @t6() nounwind {
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; CHECK: t6
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; CHECK-LABEL: t6:
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; CHECK: brk #0x1
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tail call void @llvm.trap()
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ret void
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@ -15,6 +15,7 @@ define i8 @test_i8(i8 %new) {
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; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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; CHECK-FAST-LABEL: test_i8:
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
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; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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}
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@ -28,6 +29,7 @@ define i16 @test_i16(i16 %new) {
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; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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; CHECK-FAST-LABEL: test_i16:
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
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; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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}
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@ -41,6 +43,7 @@ define i32 @test_i32(i32 %new) {
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; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
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; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
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; CHECK-FAST-LABEL: test_i32:
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32
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; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
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}
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@ -54,6 +57,7 @@ define i64 @test_i64(i64 %new) {
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; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
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; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
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; CHECK-FAST-LABEL: test_i64:
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64
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; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64
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}
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@ -64,6 +68,7 @@ define i64* @test_addr() {
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; CHECK: adrp [[HIREG:x[0-9]+]], var64
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; CHECK: add x0, [[HIREG]], :lo12:var64
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; CHECK-FAST-LABEL: test_addr:
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; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64
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; CHECK-FAST: add x0, [[HIREG]], :lo12:var64
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}
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@ -38,8 +38,8 @@ define i32 @t4(i16 zeroext %a) nounwind {
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}
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define void @foo(i8 %a, i16 %b) nounwind {
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; ARM: foo
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; THUMB: foo
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; ARM-LABEL: foo:
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; THUMB-LABEL: foo:
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;; Materialize i1 1
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; ARM: movw [[REG0:r[0-9]+]], #1
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; THUMB: movs [[REG0:r[0-9]+]], #1
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@ -87,7 +87,7 @@ declare zeroext i1 @t9();
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define i32 @t10() {
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entry:
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; ARM: @t10
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; ARM-LABEL: @t10
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; ARM-DAG: movw [[R0:l?r[0-9]*]], #0
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; ARM-DAG: movw [[R1:l?r[0-9]*]], #248
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; ARM-DAG: movw [[R2:l?r[0-9]*]], #187
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@ -114,7 +114,7 @@ entry:
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; ARM-LONG-ELF: ldr [[R:r[0-9]+]], {{\[}}[[R1]]]
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; ARM-LONG: blx [[R]]
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; THUMB: @t10
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; THUMB-LABEL: @t10
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; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0
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; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248
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; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187
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@ -146,7 +146,7 @@ define i32 @bar0(i32 %i) nounwind {
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}
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define void @foo3() uwtable {
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; ARM: @foo3
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; ARM-LABEL: @foo3
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; ARM: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr r[0-9]+, .LCPI)}}
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; ARM: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}}
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; ARM: movw {{r[0-9]+}}, #0
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@ -164,9 +164,9 @@ define void @foo3() uwtable {
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define i32 @LibCall(i32 %a, i32 %b) {
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entry:
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; ARM: LibCall
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; ARM-LABEL: LibCall:
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; ARM: bl {{___udivsi3|__aeabi_uidiv}}
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; ARM-LONG-LABEL: LibCall
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; ARM-LONG-LABEL: LibCall:
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; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}}
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; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
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@ -176,7 +176,7 @@ entry:
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; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv
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; ARM-LONG: blx r2
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; THUMB: LibCall
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; THUMB-LABEL: LibCall:
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; THUMB: bl {{___udivsi3|__aeabi_uidiv}}
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; THUMB-LONG-LABEL: LibCall
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; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}}
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@ -191,9 +191,9 @@ entry:
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define fastcc void @fast_callee(float %i) ssp {
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entry:
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; ARM: fast_callee
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; ARM-LABEL: fast_callee:
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; ARM: vmov r0, s0
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; THUMB: fast_callee
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; THUMB-LABEL: fast_callee:
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; THUMB: vmov r0, s0
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; ARM-NOVFP: fast_callee
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; ARM-NOVFP-NOT: s0
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@ -205,14 +205,14 @@ entry:
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define void @fast_caller() ssp {
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entry:
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; ARM: fast_caller
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; ARM-LABEL: fast_caller:
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; ARM: vldr s0,
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; THUMB: fast_caller
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; THUMB-LABEL: fast_caller:
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; THUMB: vldr s0,
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; ARM-NOVFP: fast_caller
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; ARM-NOVFP-LABEL: fast_caller:
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; ARM-NOVFP: movw r0, #13107
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; ARM-NOVFP: movt r0, #16611
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; THUMB-NOVFP: fast_caller
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; THUMB-NOVFP-LABEL: fast_caller:
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; THUMB-NOVFP: movw r0, #13107
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; THUMB-NOVFP: movt r0, #16611
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call fastcc void @fast_callee(float 0x401C666660000000)
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@ -221,13 +221,13 @@ entry:
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define void @no_fast_callee(float %i) ssp {
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entry:
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; ARM: no_fast_callee
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; ARM-LABEL: no_fast_callee:
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; ARM: vmov s0, r0
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; THUMB: no_fast_callee
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; THUMB-LABEL: no_fast_callee:
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; THUMB: vmov s0, r0
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; ARM-NOVFP: no_fast_callee
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; ARM-NOVFP-LABEL: no_fast_callee:
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; ARM-NOVFP-NOT: s0
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; THUMB-NOVFP: no_fast_callee
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; THUMB-NOVFP-LABEL: no_fast_callee:
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; THUMB-NOVFP-NOT: s0
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call void @print(float %i)
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ret void
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@ -235,14 +235,14 @@ entry:
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define void @no_fast_caller() ssp {
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entry:
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; ARM: no_fast_caller
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; ARM-LABEL: no_fast_caller:
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; ARM: vmov r0, s0
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; THUMB: no_fast_caller
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; THUMB-LABEL: no_fast_caller:
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; THUMB: vmov r0, s0
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; ARM-NOVFP: no_fast_caller
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; ARM-NOVFP-LABEL: no_fast_caller:
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; ARM-NOVFP: movw r0, #13107
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; ARM-NOVFP: movt r0, #16611
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; THUMB-NOVFP: no_fast_caller
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; THUMB-NOVFP-LABEL: no_fast_caller:
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; THUMB-NOVFP: movw r0, #13107
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; THUMB-NOVFP: movt r0, #16611
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call void @no_fast_callee(float 0x401C666660000000)
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@ -252,7 +252,7 @@ entry:
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declare void @bar2(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6)
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define void @call_undef_args() {
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; ARM-LABEL: call_undef_args
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; ARM-LABEL: call_undef_args:
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; ARM: movw r0, #1
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; ARM-NEXT: movw r1, #2
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; ARM-NEXT: movw r2, #3
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@ -4,7 +4,7 @@
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define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t1
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; ARM-LABEL: t1:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-16]
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@ -13,7 +13,7 @@ entry:
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define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t2
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; ARM-LABEL: t2:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -16
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-32]
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@ -22,7 +22,7 @@ entry:
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define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t3
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; ARM-LABEL: t3:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -127
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-254]
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@ -31,7 +31,7 @@ entry:
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define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t4
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; ARM-LABEL: t4:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: mvn r{{[1-9]}}, #255
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@ -42,7 +42,7 @@ entry:
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define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t5
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; ARM-LABEL: t5:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 8
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #16]
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@ -51,7 +51,7 @@ entry:
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define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t6
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; ARM-LABEL: t6:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 16
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #32]
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@ -60,7 +60,7 @@ entry:
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define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t7
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; ARM-LABEL: t7:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 127
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #254]
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@ -69,7 +69,7 @@ entry:
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define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t8
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; ARM-LABEL: t8:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 128
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: add r0, r0, #256
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@ -79,7 +79,7 @@ entry:
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define void @t9(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t9
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; ARM-LABEL: t9:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
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store i16 0, i16* %add.ptr, align 2
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; ARM: movw [[REG0:r[0-9]+]], #0
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@ -91,7 +91,7 @@ entry:
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; strh r2, [r0, r1]
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define void @t10(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t10
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; ARM-LABEL: t10:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
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store i16 0, i16* %add.ptr, align 2
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; ARM: mvn r1, #255
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@ -103,7 +103,7 @@ entry:
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define void @t11(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t11
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; ARM-LABEL: t11:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 8
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store i16 0, i16* %add.ptr, align 2
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; ARM: movw [[REG1:r[0-9]+]], #0
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@ -115,7 +115,7 @@ entry:
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; strh r2, [r0, r1]
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define void @t12(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t12
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; ARM-LABEL: t12:
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 128
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store i16 0, i16* %add.ptr, align 2
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; ARM: add [[REG0:r[0-9]+]], r0, #256
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@ -126,7 +126,7 @@ entry:
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define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t13
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; ARM-LABEL: t13:
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: ldrsb r0, [r0, #-8]
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@ -135,7 +135,7 @@ entry:
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define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t14
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; ARM-LABEL: t14:
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -255
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: ldrsb r0, [r0, #-255]
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@ -144,7 +144,7 @@ entry:
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define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t15
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; ARM-LABEL: t15:
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -256
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: mvn r{{[1-9]}}, #255
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@ -5,11 +5,11 @@
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define i32 @t1(i1 %c) nounwind readnone {
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entry:
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; ARM: t1
|
||||
; ARM-LABEL: t1:
|
||||
; ARM: tst r0, #1
|
||||
; ARM: movw r0, #10
|
||||
; ARM: moveq r0, #20
|
||||
; THUMB: t1
|
||||
; THUMB-LABEL: t1:
|
||||
; THUMB: tst.w r0, #1
|
||||
; THUMB: movw r0, #10
|
||||
; THUMB: it eq
|
||||
@ -20,10 +20,10 @@ entry:
|
||||
|
||||
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; ARM: t2
|
||||
; ARM-LABEL: t2:
|
||||
; ARM: tst {{r[0-9]+}}, #1
|
||||
; ARM: moveq {{r[0-9]+}}, #20
|
||||
; THUMB-LABEL: t2
|
||||
; THUMB-LABEL: t2:
|
||||
; THUMB: tst.w {{r[0-9]+}}, #1
|
||||
; THUMB: it eq
|
||||
; THUMB: moveq {{r[0-9]+}}, #20
|
||||
@ -33,11 +33,11 @@ entry:
|
||||
|
||||
define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
|
||||
entry:
|
||||
; ARM: t3
|
||||
; ARM-LABEL: t3:
|
||||
; ARM: tst r0, #1
|
||||
; ARM: movne r2, r1
|
||||
; ARM: add r0, r2, r1
|
||||
; THUMB: t3
|
||||
; THUMB-LABEL: t3:
|
||||
; THUMB: tst.w r0, #1
|
||||
; THUMB: it ne
|
||||
; THUMB: movne r2, r1
|
||||
@ -49,11 +49,11 @@ entry:
|
||||
|
||||
define i32 @t4(i1 %c) nounwind readnone {
|
||||
entry:
|
||||
; ARM: t4
|
||||
; ARM-LABEL: t4:
|
||||
; ARM: tst r0, #1
|
||||
; ARM: mvn r0, #9
|
||||
; ARM: mvneq r0, #0
|
||||
; THUMB-LABEL: t4
|
||||
; THUMB-LABEL: t4:
|
||||
; THUMB: tst.w r0, #1
|
||||
; THUMB: mvn r0, #9
|
||||
; THUMB: it eq
|
||||
@ -64,10 +64,10 @@ entry:
|
||||
|
||||
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; ARM: t5
|
||||
; ARM-LABEL: t5:
|
||||
; ARM: tst {{r[0-9]+}}, #1
|
||||
; ARM: mvneq {{r[0-9]+}}, #1
|
||||
; THUMB: t5
|
||||
; THUMB-LABEL: t5:
|
||||
; THUMB: tst.w {{r[0-9]+}}, #1
|
||||
; THUMB: it eq
|
||||
; THUMB: mvneq {{r[0-9]+}}, #1
|
||||
@ -78,10 +78,10 @@ entry:
|
||||
; Check one large negative immediates.
|
||||
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; ARM: t6
|
||||
; ARM-LABEL: t6:
|
||||
; ARM: tst {{r[0-9]+}}, #1
|
||||
; ARM: mvneq {{r[0-9]+}}, #978944
|
||||
; THUMB: t6
|
||||
; THUMB-LABEL: t6:
|
||||
; THUMB: tst.w {{r[0-9]+}}, #1
|
||||
; THUMB: it eq
|
||||
; THUMB: mvneq {{r[0-9]+}}, #978944
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
; load
|
||||
|
||||
define i8 @t1() nounwind {
|
||||
; ELF64: t1
|
||||
; ELF64-LABEL: t1:
|
||||
%1 = load i8, i8* @a, align 1
|
||||
; ELF64: lbz
|
||||
%2 = add nsw i8 %1, 1
|
||||
@ -32,7 +32,7 @@ define i8 @t1() nounwind {
|
||||
}
|
||||
|
||||
define i16 @t2() nounwind {
|
||||
; ELF64: t2
|
||||
; ELF64-LABEL: t2:
|
||||
%1 = load i16, i16* @b, align 2
|
||||
; ELF64: lhz
|
||||
%2 = add nsw i16 %1, 1
|
||||
@ -41,7 +41,7 @@ define i16 @t2() nounwind {
|
||||
}
|
||||
|
||||
define dso_local i32 @t3() nounwind {
|
||||
; ELF64: t3
|
||||
; ELF64-LABEL: t3:
|
||||
%1 = load i32, i32* @c, align 4
|
||||
; ELF64: lwz
|
||||
%2 = add nsw i32 %1, 1
|
||||
@ -50,7 +50,7 @@ define dso_local i32 @t3() nounwind {
|
||||
}
|
||||
|
||||
define i64 @t4() nounwind {
|
||||
; ELF64: t4
|
||||
; ELF64-LABEL: t4:
|
||||
%1 = load i64, i64* @d, align 4
|
||||
; ELF64: ld
|
||||
%2 = add nsw i64 %1, 1
|
||||
@ -59,8 +59,8 @@ define i64 @t4() nounwind {
|
||||
}
|
||||
|
||||
define dso_local float @t5() nounwind {
|
||||
; ELF64: t5
|
||||
; SPE: t5
|
||||
; ELF64-LABEL: t5:
|
||||
; SPE-LABEL: t5:
|
||||
%1 = load float, float* @e, align 4
|
||||
; ELF64: lfs
|
||||
; SPE: lwz
|
||||
@ -71,8 +71,8 @@ define dso_local float @t5() nounwind {
|
||||
}
|
||||
|
||||
define dso_local double @t6() nounwind {
|
||||
; ELF64: t6
|
||||
; SPE: t6
|
||||
; ELF64-LABEL: t6:
|
||||
; SPE-LABEL: t6:
|
||||
%1 = load double, double* @f, align 8
|
||||
; ELF64: lfd
|
||||
; VSX: lxsdx
|
||||
@ -87,7 +87,7 @@ define dso_local double @t6() nounwind {
|
||||
; store
|
||||
|
||||
define dso_local void @t7(i8 %v) nounwind {
|
||||
; ELF64: t7
|
||||
; ELF64-LABEL: t7:
|
||||
%1 = add nsw i8 %v, 1
|
||||
store i8 %1, i8* @a, align 1
|
||||
; ELF64: addis
|
||||
@ -98,7 +98,7 @@ define dso_local void @t7(i8 %v) nounwind {
|
||||
}
|
||||
|
||||
define dso_local void @t8(i16 %v) nounwind {
|
||||
; ELF64: t8
|
||||
; ELF64-LABEL: t8:
|
||||
%1 = add nsw i16 %v, 1
|
||||
store i16 %1, i16* @b, align 2
|
||||
; ELF64: addis
|
||||
@ -109,7 +109,7 @@ define dso_local void @t8(i16 %v) nounwind {
|
||||
}
|
||||
|
||||
define dso_local void @t9(i32 %v) nounwind {
|
||||
; ELF64: t9
|
||||
; ELF64-LABEL: t9:
|
||||
%1 = add nsw i32 %v, 1
|
||||
store i32 %1, i32* @c, align 4
|
||||
; ELF64: addis
|
||||
@ -120,7 +120,7 @@ define dso_local void @t9(i32 %v) nounwind {
|
||||
}
|
||||
|
||||
define dso_local void @t10(i64 %v) nounwind {
|
||||
; ELF64: t10
|
||||
; ELF64-LABEL: t10:
|
||||
%1 = add nsw i64 %v, 1
|
||||
store i64 %1, i64* @d, align 4
|
||||
; ELF64: addis
|
||||
@ -131,8 +131,8 @@ define dso_local void @t10(i64 %v) nounwind {
|
||||
}
|
||||
|
||||
define dso_local void @t11(float %v) nounwind {
|
||||
; ELF64: t11
|
||||
; SPE: t11
|
||||
; ELF64-LABEL: t11:
|
||||
; SPE-LABEL: t11:
|
||||
%1 = fadd float %v, 1.0
|
||||
store float %1, float* @e, align 4
|
||||
; ELF64: fadds
|
||||
@ -143,8 +143,8 @@ define dso_local void @t11(float %v) nounwind {
|
||||
}
|
||||
|
||||
define dso_local void @t12(double %v) nounwind {
|
||||
; ELF64: t12
|
||||
; SPE: t12
|
||||
; ELF64-LABEL: t12:
|
||||
; SPE-LABEL: t12:
|
||||
%1 = fadd double %v, 1.0
|
||||
store double %1, double* @f, align 8
|
||||
; ELF64: fadd
|
||||
@ -158,7 +158,7 @@ define dso_local void @t12(double %v) nounwind {
|
||||
|
||||
;; lwa requires an offset divisible by 4, so we need lwax here.
|
||||
define i64 @t13() nounwind {
|
||||
; ELF64: t13
|
||||
; ELF64-LABEL: t13:
|
||||
%1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1
|
||||
%2 = sext i32 %1 to i64
|
||||
; ELF64: li
|
||||
@ -170,7 +170,7 @@ define i64 @t13() nounwind {
|
||||
|
||||
;; ld requires an offset divisible by 4, so we need ldx here.
|
||||
define i64 @t14() nounwind {
|
||||
; ELF64: t14
|
||||
; ELF64-LABEL: t14:
|
||||
%1 = load i64, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
|
||||
; ELF64: li
|
||||
; ELF64: ldx
|
||||
@ -181,7 +181,7 @@ define i64 @t14() nounwind {
|
||||
|
||||
;; std requires an offset divisible by 4, so we need stdx here.
|
||||
define dso_local void @t15(i64 %v) nounwind {
|
||||
; ELF64: t15
|
||||
; ELF64-LABEL: t15:
|
||||
%1 = add nsw i64 %v, 1
|
||||
store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
|
||||
; ELF64: addis
|
||||
@ -194,7 +194,7 @@ define dso_local void @t15(i64 %v) nounwind {
|
||||
|
||||
;; ld requires an offset that fits in 16 bits, so we need ldx here.
|
||||
define i64 @t16() nounwind {
|
||||
; ELF64: t16
|
||||
; ELF64-LABEL: t16:
|
||||
%1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
|
||||
; ELF64: lis
|
||||
; ELF64: ori
|
||||
@ -206,7 +206,7 @@ define i64 @t16() nounwind {
|
||||
|
||||
;; std requires an offset that fits in 16 bits, so we need stdx here.
|
||||
define dso_local void @t17(i64 %v) nounwind {
|
||||
; ELF64: t17
|
||||
; ELF64-LABEL: t17:
|
||||
%1 = add nsw i64 %v, 1
|
||||
store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
|
||||
; ELF64: addis
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user