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[X86][GlobalISel] Support addr matching in SDAG patterns (#130445)

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addr matching was the only gatekeeper for starting selecting G_LOAD
and G_STORE using SDAG patterns.

* Introduce a complex renderer gi_addr for addr. In this patch only
the existing functionality has been implemented. The renderer's name is
the same as in SDAG: selectAddr. Apparently the type of
GIComplexOperandMatcher doesn't matter as RISCV also uses s32 for
both 64 and 32 bit pointers.
* X86SelectAddress now is used for both: pattern matching and manual
selection. As a result it accumulates all the code that previously was
distributed among different selection functions.
* Replace getLoadStoreOp with getPtrLoadStoreOp in Load/Store
selector as GlobalISel matcher or emitter can't map the pointer type
into i32/i64 types used in SDAG patterns for pointers. So the load and
store selection of pointers is still manual. getLoadStoreOp is still
present because it is used in G_FCONSTANT lowering that requires extra
efforts to select it using SDAG patterns.
* Since truncating stores are not supported, we custom legalize them by
matching types of store and MMO.
* Introduce a constant pool flag in X86AddressMode because otherwise
we need to introduce a GlobalISel copy for X86ISelAddressMode.
* Also please notice in the tests that GlobalISel prefers to fold memory
operands immediately comparing to SDAG. The reason is that GlobalISel
doesn't have target hooks in GIM_CheckIsSafeToFold. Or maybe another
check on profitability is required along with safety check that is
currently not present.
This commit is contained in:
Evgenii Kudriashov 2025-04-19 22:59:18 +02:00 committed by GitHub
parent ec6828c1ec
commit e8245d5324
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
38 changed files with 509 additions and 364 deletions
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3
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
View File

@ -66,6 +66,9 @@ public:
/// memory operations can't be reordered.
bool isUnordered() const { return getMMO().isUnordered(); }
/// Return the minimum known alignment in bytes of the actual memory
/// reference.
Align getAlign() const { return getMMO().getAlign(); }
/// Returns the size in bytes of the memory access.
LocationSize getMemSize() const { return getMMO().getSize(); }
/// Returns the size in bits of the memory access.

185
llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
View File

@ -73,6 +73,9 @@ private:
// TODO: remove after supported by Tablegen-erated instruction selection.
unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
Align Alignment) const;
// TODO: remove once p0<->i32/i64 matching is available
unsigned getPtrLoadStoreOp(const LLT &Ty, const RegisterBank &RB,
unsigned Opc) const;
bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
@ -119,6 +122,8 @@ private:
bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
ComplexRendererFns selectAddr(MachineOperand &Root) const;
// emit insert subreg instruction and insert it before MachineInstr &I
bool emitInsertSubreg(Register DstReg, Register SrcReg, MachineInstr &I,
MachineRegisterInfo &MRI, MachineFunction &MF) const;
@ -445,6 +450,25 @@ bool X86InstructionSelector::select(MachineInstr &I) {
return false;
}
unsigned X86InstructionSelector::getPtrLoadStoreOp(const LLT &Ty,
const RegisterBank &RB,
unsigned Opc) const {
assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&
"Only G_STORE and G_LOAD are expected for selection");
if (Ty.isPointer() && X86::GPRRegBankID == RB.getID()) {
bool IsLoad = (Opc == TargetOpcode::G_LOAD);
switch (Ty.getSizeInBits()) {
default:
break;
case 32:
return IsLoad ? X86::MOV32rm : X86::MOV32mr;
case 64:
return IsLoad ? X86::MOV64rm : X86::MOV64mr;
}
}
return Opc;
}
unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
const RegisterBank &RB,
unsigned Opc,
@ -460,7 +484,7 @@ unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
} else if (Ty == LLT::scalar(16)) {
if (X86::GPRRegBankID == RB.getID())
return Isload ? X86::MOV16rm : X86::MOV16mr;
} else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
} else if (Ty == LLT::scalar(32)) {
if (X86::GPRRegBankID == RB.getID())
return Isload ? X86::MOV32rm : X86::MOV32mr;
if (X86::VECRRegBankID == RB.getID())
@ -472,7 +496,7 @@ unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
X86::MOVSSmr);
if (X86::PSRRegBankID == RB.getID())
return Isload ? X86::LD_Fp32m : X86::ST_Fp32m;
} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
} else if (Ty == LLT::scalar(64)) {
if (X86::GPRRegBankID == RB.getID())
return Isload ? X86::MOV64rm : X86::MOV64mr;
if (X86::VECRRegBankID == RB.getID())
@ -530,30 +554,76 @@ unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
}
// Fill in an address from the given instruction.
static void X86SelectAddress(const MachineInstr &I,
static bool X86SelectAddress(MachineInstr &I, const X86TargetMachine &TM,
const MachineRegisterInfo &MRI,
X86AddressMode &AM) {
assert(I.getOperand(0).isReg() && "unsupported opperand.");
const X86Subtarget &STI, X86AddressMode &AM) {
assert(I.getOperand(0).isReg() && "unsupported operand.");
assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
"unsupported type.");
if (I.getOpcode() == TargetOpcode::G_PTR_ADD) {
switch (I.getOpcode()) {
default:
break;
case TargetOpcode::G_FRAME_INDEX:
AM.Base.FrameIndex = I.getOperand(1).getIndex();
AM.BaseType = X86AddressMode::FrameIndexBase;
return true;
case TargetOpcode::G_PTR_ADD: {
if (auto COff = getIConstantVRegSExtVal(I.getOperand(2).getReg(), MRI)) {
int64_t Imm = *COff;
if (isInt<32>(Imm)) { // Check for displacement overflow.
AM.Disp = static_cast<int32_t>(Imm);
AM.Base.Reg = I.getOperand(1).getReg();
return;
return true;
}
}
} else if (I.getOpcode() == TargetOpcode::G_FRAME_INDEX) {
AM.Base.FrameIndex = I.getOperand(1).getIndex();
AM.BaseType = X86AddressMode::FrameIndexBase;
return;
break;
}
case TargetOpcode::G_GLOBAL_VALUE: {
auto GV = I.getOperand(1).getGlobal();
if (GV->isThreadLocal()) {
return false; // TODO: we don't support TLS yet.
}
// Can't handle alternate code models yet.
if (TM.getCodeModel() != CodeModel::Small)
return false;
AM.GV = GV;
AM.GVOpFlags = STI.classifyGlobalReference(GV);
// TODO: The ABI requires an extra load. not supported yet.
if (isGlobalStubReference(AM.GVOpFlags))
return false;
// TODO: This reference is relative to the pic base. not supported yet.
if (isGlobalRelativeToPICBase(AM.GVOpFlags))
return false;
if (STI.isPICStyleRIPRel()) {
// Use rip-relative addressing.
assert(AM.Base.Reg == 0 && AM.IndexReg == 0 &&
"RIP-relative addresses can't have additional register operands");
AM.Base.Reg = X86::RIP;
}
return true;
}
case TargetOpcode::G_CONSTANT_POOL: {
// TODO: Need a separate move for Large model
if (TM.getCodeModel() == CodeModel::Large)
return false;
AM.GVOpFlags = STI.classifyLocalReference(nullptr);
if (AM.GVOpFlags == X86II::MO_GOTOFF)
AM.Base.Reg = STI.getInstrInfo()->getGlobalBaseReg(I.getMF());
else if (STI.is64Bit())
AM.Base.Reg = X86::RIP;
AM.CP = true;
AM.Disp = I.getOperand(1).getIndex();
return true;
}
}
// Default behavior.
AM.Base.Reg = I.getOperand(0).getReg();
return true;
}
bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
@ -586,36 +656,18 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
}
}
unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign());
unsigned NewOpc = getPtrLoadStoreOp(Ty, RB, Opc);
if (NewOpc == Opc)
return false;
I.setDesc(TII.get(NewOpc));
MachineInstrBuilder MIB(MF, I);
const MachineInstr *Ptr = MRI.getVRegDef(I.getOperand(1).getReg());
if (Ptr->getOpcode() == TargetOpcode::G_CONSTANT_POOL) {
assert(Opc == TargetOpcode::G_LOAD &&
"Only G_LOAD from constant pool is expected");
// TODO: Need a separate move for Large model
if (TM.getCodeModel() == CodeModel::Large)
return false;
unsigned char OpFlag = STI.classifyLocalReference(nullptr);
Register PICBase;
if (OpFlag == X86II::MO_GOTOFF)
PICBase = TII.getGlobalBaseReg(&MF);
else if (STI.is64Bit())
PICBase = X86::RIP;
I.removeOperand(1);
addConstantPoolReference(MIB, Ptr->getOperand(1).getIndex(), PICBase,
OpFlag);
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
MachineInstr *Ptr = MRI.getVRegDef(I.getOperand(1).getReg());
X86AddressMode AM;
X86SelectAddress(*Ptr, MRI, AM);
if (!X86SelectAddress(*Ptr, TM, MRI, STI, AM))
return false;
if (Opc == TargetOpcode::G_LOAD) {
I.removeOperand(1);
addFullAddress(MIB, AM);
@ -673,33 +725,10 @@ bool X86InstructionSelector::selectGlobalValue(MachineInstr &I,
assert((I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE) &&
"unexpected instruction");
auto GV = I.getOperand(1).getGlobal();
if (GV->isThreadLocal()) {
return false; // TODO: we don't support TLS yet.
}
// Can't handle alternate code models yet.
if (TM.getCodeModel() != CodeModel::Small)
return false;
X86AddressMode AM;
AM.GV = GV;
AM.GVOpFlags = STI.classifyGlobalReference(GV);
// TODO: The ABI requires an extra load. not supported yet.
if (isGlobalStubReference(AM.GVOpFlags))
if (!X86SelectAddress(I, TM, MRI, STI, AM))
return false;
// TODO: This reference is relative to the pic base. not supported yet.
if (isGlobalRelativeToPICBase(AM.GVOpFlags))
return false;
if (STI.isPICStyleRIPRel()) {
// Use rip-relative addressing.
assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
AM.Base.Reg = X86::RIP;
}
const Register DefReg = I.getOperand(0).getReg();
LLT Ty = MRI.getType(DefReg);
unsigned NewOpc = getLeaOP(Ty, STI);
@ -1880,6 +1909,46 @@ bool X86InstructionSelector::selectSelect(MachineInstr &I,
return true;
}
InstructionSelector::ComplexRendererFns
X86InstructionSelector::selectAddr(MachineOperand &Root) const {
MachineInstr *MI = Root.getParent();
MachineIRBuilder MIRBuilder(*MI);
MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
MachineInstr *Ptr = MRI.getVRegDef(Root.getReg());
X86AddressMode AM;
X86SelectAddress(*Ptr, TM, MRI, STI, AM);
if (AM.IndexReg)
return std::nullopt;
return {// Base
{[=](MachineInstrBuilder &MIB) {
if (AM.BaseType == X86AddressMode::RegBase)
MIB.addUse(AM.Base.Reg);
else {
assert(AM.BaseType == X86AddressMode::FrameIndexBase &&
"Unknown type of address base");
MIB.addFrameIndex(AM.Base.FrameIndex);
}
},
// Scale
[=](MachineInstrBuilder &MIB) { MIB.addImm(AM.Scale); },
// Index
[=](MachineInstrBuilder &MIB) { MIB.addUse(0); },
// Disp
[=](MachineInstrBuilder &MIB) {
if (AM.GV)
MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
else if (AM.CP)
MIB.addConstantPoolIndex(AM.Disp, 0, AM.GVOpFlags);
else
MIB.addImm(AM.Disp);
},
// Segment
[=](MachineInstrBuilder &MIB) { MIB.addUse(0); }}};
}
InstructionSelector *
llvm::createX86InstructionSelector(const X86TargetMachine &TM,
const X86Subtarget &Subtarget,

47
llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
View File

@ -373,22 +373,16 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
// load/store: add more corner cases
for (unsigned Op : {G_LOAD, G_STORE}) {
auto &Action = getActionDefinitionsBuilder(Op);
Action.legalForTypesWithMemDesc({{s8, p0, s1, 1},
{s8, p0, s8, 1},
{s16, p0, s8, 1},
Action.legalForTypesWithMemDesc({{s8, p0, s8, 1},
{s16, p0, s16, 1},
{s32, p0, s8, 1},
{s32, p0, s16, 1},
{s32, p0, s32, 1},
{s80, p0, s80, 1},
{p0, p0, p0, 1},
{v4s8, p0, v4s8, 1}});
if (Is64Bit)
Action.legalForTypesWithMemDesc({{s64, p0, s8, 1},
{s64, p0, s16, 1},
{s64, p0, s32, 1},
{s64, p0, s64, 1},
{v2s32, p0, v2s32, 1}});
Action.legalForTypesWithMemDesc(
{{s64, p0, s64, 1}, {v2s32, p0, v2s32, 1}});
if (HasSSE1)
Action.legalForTypesWithMemDesc({{v4s32, p0, v4s32, 1}});
if (HasSSE2)
@ -407,6 +401,21 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
{v32s16, p0, v32s16, 1},
{v16s32, p0, v16s32, 1},
{v8s64, p0, v8s64, 1}});
// X86 supports extending loads but not stores for GPRs
if (Op == G_LOAD) {
Action.legalForTypesWithMemDesc({{s8, p0, s1, 1},
{s16, p0, s8, 1},
{s32, p0, s8, 1},
{s32, p0, s16, 1}});
if (Is64Bit)
Action.legalForTypesWithMemDesc(
{{s64, p0, s8, 1}, {s64, p0, s16, 1}, {s64, p0, s32, 1}});
} else {
Action.customIf([=](const LegalityQuery &Query) {
return Query.Types[0] != Query.MMODescrs[0].MemoryTy;
});
}
Action.widenScalarToNextPow2(0, /*Min=*/8)
.clampScalar(0, s8, sMaxScalar)
.scalarize(0);
@ -660,6 +669,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeFPTOUI(MI, MRI, Helper);
case TargetOpcode::G_UITOFP:
return legalizeUITOFP(MI, MRI, Helper);
case TargetOpcode::G_STORE:
return legalizeNarrowingStore(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
@ -754,6 +765,22 @@ bool X86LegalizerInfo::legalizeUITOFP(MachineInstr &MI,
return false;
}
bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const {
auto &Store = cast<GStore>(MI);
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
MachineMemOperand &MMO = **Store.memoperands_begin();
MachineFunction &MF = MIRBuilder.getMF();
LLT ValTy = MRI.getType(Store.getValueReg());
auto *NewMMO = MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), ValTy);
Helper.Observer.changingInstr(Store);
Store.setMemRefs(MF, {NewMMO});
Helper.Observer.changedInstr(Store);
return true;
}
bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;

3
llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
View File

@ -45,6 +45,9 @@ private:
bool legalizeUITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
bool legalizeNarrowingStore(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif

1
llvm/lib/Target/X86/X86InstrBuilder.h
View File

@ -54,6 +54,7 @@ struct X86AddressMode {
int Disp = 0;
const GlobalValue *GV = nullptr;
unsigned GVOpFlags = 0;
bool CP = false;
void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);

34
llvm/lib/Target/X86/X86InstrFragments.td
View File

@ -354,6 +354,8 @@ def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd,
// Define X86-specific addressing mode.
let WantsParent = true in
def addr : ComplexPattern<iPTR, 5, "selectAddr">;
def gi_addr : GIComplexOperandMatcher<s32, "selectAddr">,
GIComplexPatternEquiv<addr>;
def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
[add, sub, mul, X86mul_imm, shl, or, xor, frameindex],
[]>;
@ -444,7 +446,11 @@ def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{
//
def imm_su : PatLeaf<(imm), [{
return !shouldAvoidImmediateInstFormsForSize(N);
}]>;
}]> {
// TODO : introduce the same check as in SDAG
let GISelPredicateCode = [{ return true; }];
}
def i64immSExt32_su : PatLeaf<(i64immSExt32), [{
return !shouldAvoidImmediateInstFormsForSize(N);
}]>;
@ -500,7 +506,9 @@ def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{
ISD::LoadExtType ExtType = LD->getExtensionType();
return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD ||
ExtType == ISD::ZEXTLOAD;
}]>;
}]> {
let GISelPredicateCode = [{ return isa<GLoad>(MI); }];
}
// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
// known to be 32-bit aligned or better. Ditto for i8 to i16.
@ -512,7 +520,16 @@ def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad)
return LD->getAlign() >= 2 && LD->isSimple();
return false;
}]>;
}]> {
let GISelPredicateCode = [{
auto &Load = cast<GLoad>(MI);
LLT Ty = MRI.getType(Load.getDstReg());
// Non extending load has MMO and destination types of the same size
if (Load.getMemSizeInBits() == Ty.getSizeInBits())
return true;
return Load.getAlign() >= 2 && Load.isSimple();
}];
}
def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
LoadSDNode *LD = cast<LoadSDNode>(N);
@ -522,7 +539,16 @@ def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad)
return LD->getAlign() >= 4 && LD->isSimple();
return false;
}]>;
}]> {
let GISelPredicateCode = [{
auto &Load = cast<GLoad>(MI);
LLT Ty = MRI.getType(Load.getDstReg());
// Non extending load has MMO and destination types of the same size
if (Load.getMemSizeInBits() == Ty.getSizeInBits())
return true;
return Load.getAlign() >= 4 && Load.isSimple();
}];
}
def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
def loadf16 : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>;

14
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
View File

@ -1008,13 +1008,23 @@ def alignedstore : PatFrag<(ops node:$val, node:$ptr),
(store node:$val, node:$ptr), [{
auto *St = cast<StoreSDNode>(N);
return St->getAlign() >= St->getMemoryVT().getStoreSize();
}]>;
}]> {
let GISelPredicateCode = [{
auto &LdSt = cast<GLoadStore>(MI);
return LdSt.getAlign() >= LdSt.getMemSize().getValue();
}];
}
// Like 'load', but always requires vector size alignment.
def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
auto *Ld = cast<LoadSDNode>(N);
return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize();
}]>;
}]> {
let GISelPredicateCode = [{
auto &LdSt = cast<GLoadStore>(MI);
return LdSt.getAlign() >= LdSt.getMemSize().getValue();
}];
}
// 128-bit aligned load pattern fragments
// NOTE: all 128-bit integer vector loads are promoted to v2i64

12
llvm/test/CodeGen/X86/GlobalISel/GV.ll
View File

@ -36,26 +36,22 @@ entry:
define dso_local i32 @test_global_valv() #3 {
; X64-LABEL: test_global_valv:
; X64: # %bb.0: # %entry
; X64-NEXT: leaq g_int, %rax
; X64-NEXT: movl (%rax), %eax
; X64-NEXT: movl g_int, %eax
; X64-NEXT: retq
;
; X64_DARWIN_PIC-LABEL: test_global_valv:
; X64_DARWIN_PIC: ## %bb.0: ## %entry
; X64_DARWIN_PIC-NEXT: leaq _g_int(%rip), %rax
; X64_DARWIN_PIC-NEXT: movl (%rax), %eax
; X64_DARWIN_PIC-NEXT: movl _g_int(%rip), %eax
; X64_DARWIN_PIC-NEXT: retq
;
; X32-LABEL: test_global_valv:
; X32: # %bb.0: # %entry
; X32-NEXT: leal g_int, %eax
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl g_int, %eax
; X32-NEXT: retl
;
; X32ABI-LABEL: test_global_valv:
; X32ABI: # %bb.0: # %entry
; X32ABI-NEXT: leal g_int, %eax
; X32ABI-NEXT: movl (%eax), %eax
; X32ABI-NEXT: movl g_int, %eax
; X32ABI-NEXT: retq
entry:
%0 = load i32, ptr @g_int, align 4

8
llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll
View File

@ -80,8 +80,8 @@ define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
;
; X86-LABEL: test_add_i16:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addw %cx, %ax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
@ -100,8 +100,8 @@ define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
;
; X86-LABEL: test_add_i8:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addb %cl, %al
; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl

7
llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
View File

@ -32,7 +32,7 @@ define i64 @test_ret_i64() {
define i8 @test_arg_i8(i8 %a) {
; X32-LABEL: test_arg_i8:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: # kill: def $al killed $al killed $eax
; X32-NEXT: retl
;
@ -47,7 +47,7 @@ define i8 @test_arg_i8(i8 %a) {
define i16 @test_arg_i16(i16 %a) {
; X32-LABEL: test_arg_i16:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: # kill: def $ax killed $ax killed $eax
; X32-NEXT: retl
;
@ -230,8 +230,7 @@ define i32 @test_simple_return_callee() {
; X32: # %bb.0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: movl $5, %eax
; X32-NEXT: movl %eax, (%esp)
; X32-NEXT: movl $5, (%esp)
; X32-NEXT: calll simple_return_callee
; X32-NEXT: addl %eax, %eax
; X32-NEXT: addl $12, %esp

56
llvm/test/CodeGen/X86/GlobalISel/isel-fcmp-i686.mir
View File

@ -17,8 +17,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_oeq
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; GISEL-X86-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
@ -47,8 +47,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ogt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -75,8 +75,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_oge
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -103,8 +103,8 @@ fixedStack:
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_olt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -131,8 +131,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ole
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -158,8 +158,8 @@ fixedStack:
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_one
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -186,8 +186,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ord
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -213,8 +213,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_uno
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -241,8 +241,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ueq
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -270,8 +270,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ugt
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -298,8 +298,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_uge
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m1]], [[LD_Fp64m]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -327,8 +327,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ult
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -355,8 +355,8 @@ stack: []
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_ule
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
; GISEL-X86-NEXT: $al = COPY [[SETCCr]]
@ -382,8 +382,8 @@ fixedStack:
body: |
bb.1.entry:
; GISEL-X86-LABEL: name: fcmp_double_une
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86: [[LD_Fp64m:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0)
; GISEL-X86-NEXT: [[LD_Fp64m1:%[0-9]+]]:rfp64 = nofpexcept LD_Fp64m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s64) from %fixed-stack.0 + 8)
; GISEL-X86-NEXT: UCOM_FpIr64 [[LD_Fp64m]], [[LD_Fp64m1]], implicit-def $eflags, implicit-def $fpsw, implicit $fpcw
; GISEL-X86-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
; GISEL-X86-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags

2
llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
View File

@ -17,7 +17,7 @@ body: |
; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s8))
; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store (s32))

2
llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
View File

@ -17,7 +17,7 @@ body: |
; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s8))
; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store (s32))

2
llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
View File

@ -55,7 +55,7 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]]
; CHECK-NEXT: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK-NEXT: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s8))
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)

4
llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
View File

@ -22,7 +22,7 @@ body: |
; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
; X32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; X32-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
; X32-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
; X32-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s8))
; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
; X32-NEXT: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
; X32-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
@ -35,7 +35,7 @@ body: |
; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
; X64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; X64-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
; X64-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
; X64-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s8))
; X64-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
; X64-NEXT: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
; X64-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)

4
llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
View File

@ -12,7 +12,7 @@ body: |
; X64-LABEL: name: test_implicit_def
; X64: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; X64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; X64-NEXT: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s1))
; X64-NEXT: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s8))
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; X64-NEXT: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store (s8))
; X64-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@ -24,7 +24,7 @@ body: |
; X32-LABEL: name: test_implicit_def
; X32: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; X32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; X32-NEXT: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s1))
; X32-NEXT: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s8))
; X32-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; X32-NEXT: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store (s8))
; X32-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF

6
llvm/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll
View File

@ -47,7 +47,7 @@ define i32 @test_load_i32(ptr %p1) {
define ptr @test_store_i1(i1 %val, ptr %p1) {
; CHECK-LABEL: test_store_i1:
; CHECK: # %bb.0:
; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movzbl 4(%esp), %ecx
; CHECK-NEXT: movl 8(%esp), %eax
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movb %cl, (%eax)
@ -59,7 +59,7 @@ define ptr @test_store_i1(i1 %val, ptr %p1) {
define ptr @test_store_i8(i8 %val, ptr %p1) {
; CHECK-LABEL: test_store_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movzbl 4(%esp), %ecx
; CHECK-NEXT: movl 8(%esp), %eax
; CHECK-NEXT: movb %cl, (%eax)
; CHECK-NEXT: retl
@ -70,7 +70,7 @@ define ptr @test_store_i8(i8 %val, ptr %p1) {
define ptr @test_store_i16(i16 %val, ptr %p1) {
; CHECK-LABEL: test_store_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movzwl 4(%esp), %ecx
; CHECK-NEXT: movl 8(%esp), %eax
; CHECK-NEXT: movw %cx, (%eax)
; CHECK-NEXT: retl

12
llvm/test/CodeGen/X86/GlobalISel/mul-scalar.ll
View File

@ -11,8 +11,8 @@ define i8 @test_mul_i8(i8 %arg1, i8 %arg2) nounwind {
;
; X86-LABEL: test_mul_i8:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cbtw
; X86-NEXT: imulb %cl
; X86-NEXT: retl
@ -30,8 +30,8 @@ define i16 @test_mul_i16(i16 %arg1, i16 %arg2) nounwind {
;
; X86-LABEL: test_mul_i16:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: imulw %cx, %ax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
@ -69,11 +69,11 @@ define i64 @test_mul_i64(i64 %arg1, i64 %arg2) nounwind {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: imull %eax, %esi
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: imull %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: imull %edx, %edi
; X86-NEXT: imull {{[0-9]+}}(%esp), %esi
; X86-NEXT: addl %edi, %esi
; X86-NEXT: mull %edx
; X86-NEXT: addl %esi, %edx

8
llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
View File

@ -61,17 +61,15 @@ legalized: true
regBankSelected: true
# X32ALL: registers:
# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
# X32ALL-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
# X32: %1:gr32 = LEA32r $noreg, 1, $noreg, @g_int, $noreg
# X32-NEXT: %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load (s32) from @g_int)
# X32: %0:gr32 = MOV32rm $noreg, 1, $noreg, @g_int, $noreg :: (load (s32) from @g_int)
# X32-NEXT: $eax = COPY %0
# X32-NEXT: RET 0, implicit $eax
#
# X32ABI: %1:gr32 = LEA64_32r $noreg, 1, $noreg, @g_int, $noreg
# X32ABI-NEXT: %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load (s32) from @g_int)
# X32ABI: %0:gr32 = MOV32rm $noreg, 1, $noreg, @g_int, $noreg :: (load (s32) from @g_int)
# X32ABI-NEXT: $eax = COPY %0
# X32ABI-NEXT: RET 0, implicit $eax
body: |

8
llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
View File

@ -59,18 +59,16 @@ legalized: true
regBankSelected: true
# X64ALL: registers:
# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
# X64ALL-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
#
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
# X64: %1:gr64 = LEA64r $noreg, 1, $noreg, @g_int, $noreg
# X64-NEXT: %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load (s32) from @g_int)
# X64: %0:gr32 = MOV32rm $noreg, 1, $noreg, @g_int, $noreg :: (load (s32) from @g_int)
# X64-NEXT: $eax = COPY %0
# X64-NEXT: RET 0, implicit $eax
#
# X64_DARWIN_PIC: %1:gr64 = LEA64r $rip, 1, $noreg, @g_int, $noreg
# X64_DARWIN_PIC-NEXT: %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load (s32) from @g_int)
# X64_DARWIN_PIC: %0:gr32 = MOV32rm $rip, 1, $noreg, @g_int, $noreg :: (load (s32) from @g_int)
# X64_DARWIN_PIC-NEXT: $eax = COPY %0
# X64_DARWIN_PIC-NEXT: RET 0, implicit $eax
#

18
llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
View File

@ -1,7 +1,7 @@
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512F,SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,NO_AVX512F,AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512ALL,AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512ALL,AVX512VL
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL
--- |
define <4 x i32> @test_load_v4i32_noalign(ptr %p1) {
@ -37,7 +37,7 @@ registers:
# ALL: %0:gr64 = COPY $rdi
# SSE: %1:vr128 = MOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)
# AVX: %1:vr128 = VMOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)
# AVX512F: %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)
# AVX512F: %1:vr128 = VMOVUPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)
# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1, align 1)
# ALL: $xmm0 = COPY %1
body: |
@ -62,7 +62,7 @@ registers:
# ALL: %0:gr64 = COPY $rdi
# SSE: %1:vr128 = MOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)
# AVX: %1:vr128 = VMOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)
# AVX512F: %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)
# AVX512F: %1:vr128 = VMOVAPSrm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)
# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, $noreg, 0, $noreg :: (load (<4 x s32>) from %ir.p1)
# ALL: $xmm0 = COPY %1
body: |
@ -85,11 +85,12 @@ registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# NO_AVX512F: %0:vr128 = COPY $xmm0
# AVX512ALL: %0:vr128x = COPY $xmm0
# AVX512F: %0:vr128 = COPY $xmm0
# AVX512VL: %0:vr128x = COPY $xmm0
# ALL: %1:gr64 = COPY $rdi
# SSE: MOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)
# AVX: VMOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)
# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)
# AVX512F: VMOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)
# AVX512VL: VMOVAPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1)
# ALL: $rax = COPY %1
body: |
@ -113,11 +114,12 @@ registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# NO_AVX512F: %0:vr128 = COPY $xmm0
# AVX512ALL: %0:vr128x = COPY $xmm0
# AVX512F: %0:vr128 = COPY $xmm0
# AVX512VL: %0:vr128x = COPY $xmm0
# ALL: %1:gr64 = COPY $rdi
# SSE: MOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)
# AVX: VMOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)
# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)
# AVX512F: VMOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)
# AVX512VL: VMOVUPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store (<4 x s32>) into %ir.p1, align 1)
# ALL: $rax = COPY %1
body: |

21
llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
View File

@ -38,7 +38,8 @@ regBankSelected: true
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@ -48,7 +49,7 @@ registers:
# NO_AVX512F-NEXT: RET 0, implicit $ymm0
#
# AVX512F: %0:gr64 = COPY $rdi
# AVX512F-NEXT: %1:vr256x = VMOVUPSZ256rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load (<8 x s32>) from %ir.p1, align 1)
# AVX512F-NEXT: %1:vr256 = VMOVUPSYrm %0, 1, $noreg, 0, $noreg :: (load (<8 x s32>) from %ir.p1, align 1)
# AVX512F-NEXT: $ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit $ymm0
#
@ -81,7 +82,7 @@ registers:
# NO_AVX512F-NEXT: RET 0, implicit $ymm0
#
# AVX512F: %0:gr64 = COPY $rdi
# AVX512F-NEXT: %1:vr256x = VMOVAPSZ256rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load (<8 x s32>) from %ir.p1)
# AVX512F-NEXT: %1:vr256 = VMOVAPSYrm %0, 1, $noreg, 0, $noreg :: (load (<8 x s32>) from %ir.p1)
# AVX512F-NEXT: $ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit $ymm0
#
@ -110,7 +111,8 @@ regBankSelected: true
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
@ -120,9 +122,9 @@ registers:
# NO_AVX512F-NEXT: VMOVUPSYmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1, align 1)
# NO_AVX512F-NEXT: RET 0
#
# AVX512F: %0:vr256x = COPY $ymm0
# AVX512F: %0:vr256 = COPY $ymm0
# AVX512F-NEXT: %1:gr64 = COPY $rdi
# AVX512F-NEXT: VMOVUPSZ256mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1, align 1)
# AVX512F-NEXT: VMOVUPSYmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1, align 1)
# AVX512F-NEXT: RET 0
#
# AVX512VL: %0:vr256x = COPY $ymm0
@ -150,7 +152,8 @@ regBankSelected: true
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
@ -160,9 +163,9 @@ registers:
# NO_AVX512F-NEXT: VMOVAPSYmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1)
# NO_AVX512F-NEXT: RET 0
#
# AVX512F: %0:vr256x = COPY $ymm0
# AVX512F: %0:vr256 = COPY $ymm0
# AVX512F-NEXT: %1:gr64 = COPY $rdi
# AVX512F-NEXT: VMOVAPSZ256mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1)
# AVX512F-NEXT: VMOVAPSYmr %1, 1, $noreg, 0, $noreg, %0 :: (store (<8 x s32>) into %ir.p1)
# AVX512F-NEXT: RET 0
#
# AVX512VL: %0:vr256x = COPY $ymm0

4
llvm/test/CodeGen/X86/GlobalISel/sqrt.mir
View File

@ -12,7 +12,7 @@ fixedStack:
body: |
bb.1:
; GISEL-I686-LABEL: name: test_sqrt_f32
; GISEL-I686: [[LD_Fp32m:%[0-9]+]]:rfp32 = LD_Fp32m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s32) from %fixed-stack.0, align 16)
; GISEL-I686: [[LD_Fp32m:%[0-9]+]]:rfp32 = nofpexcept LD_Fp32m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s32) from %fixed-stack.0, align 16)
; GISEL-I686-NEXT: [[SQRT_Fp32_:%[0-9]+]]:rfp32 = nofpexcept SQRT_Fp32 [[LD_Fp32m]], implicit-def dead $fpsw, implicit $fpcw
; GISEL-I686-NEXT: $fp0 = COPY [[SQRT_Fp32_]]
; GISEL-I686-NEXT: RET 0, implicit $fp0
@ -55,7 +55,7 @@ fixedStack:
body: |
bb.1:
; GISEL-I686-LABEL: name: test_sqrt_f80
; GISEL-I686: [[LD_Fp80m:%[0-9]+]]:rfp80 = LD_Fp80m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def $fpsw, implicit $fpcw :: (invariant load (s80) from %fixed-stack.0, align 16)
; GISEL-I686: [[LD_Fp80m:%[0-9]+]]:rfp80 = nofpexcept LD_Fp80m %fixed-stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (invariant load (s80) from %fixed-stack.0, align 16)
; GISEL-I686-NEXT: [[SQRT_Fp80_:%[0-9]+]]:rfp80 = nofpexcept SQRT_Fp80 [[LD_Fp80m]], implicit-def dead $fpsw, implicit $fpcw
; GISEL-I686-NEXT: $fp0 = COPY [[SQRT_Fp80_]]
; GISEL-I686-NEXT: RET 0, implicit $fp0

8
llvm/test/CodeGen/X86/GlobalISel/sub-scalar.ll
View File

@ -79,8 +79,8 @@ define i16 @test_sub_i16(i16 %arg1, i16 %arg2) {
;
; X86-LABEL: test_sub_i16:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subw %cx, %ax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
@ -98,8 +98,8 @@ define i8 @test_sub_i8(i8 %arg1, i8 %arg2) {
;
; X86-LABEL: test_sub_i8:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: subb %cl, %al
; X86-NEXT: # kill: def $al killed $al killed $eax
; X86-NEXT: retl

80
llvm/test/CodeGen/X86/isel-and.ll
View File

@ -21,8 +21,8 @@ define i1 @and_i1(i1 %a, i1 %b) {
;
; GISEL-X86-LABEL: and_i1:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -65,8 +65,8 @@ define i8 @and_i8(i8 %a, i8 %b) {
;
; GISEL-X86-LABEL: and_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -110,8 +110,8 @@ define i16 @and_i16(i16 %a, i16 %b) {
;
; GISEL-X86-LABEL: and_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andw %cx, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -229,7 +229,7 @@ define i8 @and_imm8_i8(i8 %a) {
;
; GISEL-X86-LABEL: and_imm8_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andb $1, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -260,7 +260,7 @@ define i16 @and_imm8_i16(i16 %a) {
;
; GISEL-X86-LABEL: and_imm8_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andw $6, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -290,11 +290,23 @@ define i16 @and_imm8_i16(i16 %a) {
}
define i32 @and_imm8_i32(i32 %a) {
; X86-LABEL: and_imm8_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andl $-5, %eax
; X86-NEXT: retl
; SDAG-X86-LABEL: and_imm8_i32:
; SDAG-X86: # %bb.0:
; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; SDAG-X86-NEXT: andl $-5, %eax
; SDAG-X86-NEXT: retl
;
; FASTISEL-X86-LABEL: and_imm8_i32:
; FASTISEL-X86: # %bb.0:
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: andl $-5, %eax
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: and_imm8_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-5, %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm8_i32:
; X64: # %bb.0:
@ -322,10 +334,10 @@ define i64 @and_imm8_i64(i64 %a) {
;
; GISEL-X86-LABEL: and_imm8_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: andl $1, %eax
; GISEL-X86-NEXT: andl $0, %edx
; GISEL-X86-NEXT: movl $1, %eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; SDAG-X64-LABEL: and_imm8_i64:
@ -365,7 +377,7 @@ define i16 @and_imm16_i16(i16 %a) {
;
; GISEL-X86-LABEL: and_imm16_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andw $1023, %ax # imm = 0x3FF
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -409,8 +421,8 @@ define i32 @and_imm16_i32(i32 %a) {
;
; GISEL-X86-LABEL: and_imm16_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: movl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm16_i32:
@ -439,10 +451,10 @@ define i64 @and_imm16_i64(i64 %a) {
;
; GISEL-X86-LABEL: and_imm16_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: andl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: andl $-1, %edx
; GISEL-X86-NEXT: movl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm16_i64:
@ -469,8 +481,8 @@ define i32 @and_imm32_i32(i32 %a) {
;
; GISEL-X86-LABEL: and_imm32_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: movl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm32_i32:
@ -499,10 +511,10 @@ define i64 @and_imm32_i64(i64 %a) {
;
; GISEL-X86-LABEL: and_imm32_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: andl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: andl $-1, %edx
; GISEL-X86-NEXT: movl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm32_i64:
@ -533,10 +545,10 @@ define i64 @and_imm64_i64(i64 %a) {
;
; GISEL-X86-LABEL: and_imm64_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: andl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: andl $-2, %edx
; GISEL-X86-NEXT: movl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: movl $-2, %edx
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: and_imm64_i64:

48
llvm/test/CodeGen/X86/isel-buildvector-sse.ll
View File

@ -23,22 +23,14 @@ define <8 x i32> @test_vector_v8i32() {
; SSE-X64-GISEL-LABEL: test_vector_v8i32:
; SSE-X64-GISEL: # %bb.0:
; SSE-X64-GISEL-NEXT: movq %rdi, %rax
; SSE-X64-GISEL-NEXT: movl $128100944, %ecx # imm = 0x7A2AA50
; SSE-X64-GISEL-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
; SSE-X64-GISEL-NEXT: movl $-408980432, %esi # imm = 0xE79F7430
; SSE-X64-GISEL-NEXT: movl $708630551, %edi # imm = 0x2A3CD817
; SSE-X64-GISEL-NEXT: movl $-871899055, %r8d # imm = 0xCC07E051
; SSE-X64-GISEL-NEXT: movl $-633489957, %r9d # imm = 0xDA3DB5DB
; SSE-X64-GISEL-NEXT: movl $591019567, %r10d # imm = 0x233A3E2F
; SSE-X64-GISEL-NEXT: movl $708632899, %r11d # imm = 0x2A3CE143
; SSE-X64-GISEL-NEXT: movl %ecx, (%rax)
; SSE-X64-GISEL-NEXT: movl %edx, 4(%rax)
; SSE-X64-GISEL-NEXT: movl %esi, 8(%rax)
; SSE-X64-GISEL-NEXT: movl %edi, 12(%rax)
; SSE-X64-GISEL-NEXT: movl %r8d, 16(%rax)
; SSE-X64-GISEL-NEXT: movl %r9d, 20(%rax)
; SSE-X64-GISEL-NEXT: movl %r10d, 24(%rax)
; SSE-X64-GISEL-NEXT: movl %r11d, 28(%rax)
; SSE-X64-GISEL-NEXT: movl $128100944, (%rdi) # imm = 0x7A2AA50
; SSE-X64-GISEL-NEXT: movl $-632258670, 4(%rdi) # imm = 0xDA507F92
; SSE-X64-GISEL-NEXT: movl $-408980432, 8(%rdi) # imm = 0xE79F7430
; SSE-X64-GISEL-NEXT: movl $708630551, 12(%rdi) # imm = 0x2A3CD817
; SSE-X64-GISEL-NEXT: movl $-871899055, 16(%rdi) # imm = 0xCC07E051
; SSE-X64-GISEL-NEXT: movl $-633489957, 20(%rdi) # imm = 0xDA3DB5DB
; SSE-X64-GISEL-NEXT: movl $591019567, 24(%rdi) # imm = 0x233A3E2F
; SSE-X64-GISEL-NEXT: movl $708632899, 28(%rdi) # imm = 0x2A3CE143
; SSE-X64-GISEL-NEXT: retq
;
; SSE-X86-LABEL: test_vector_v8i32:
@ -57,22 +49,14 @@ define <8 x i32> @test_vector_v8i32() {
; SSE-X86-GISEL-LABEL: test_vector_v8i32:
; SSE-X86-GISEL: # %bb.0:
; SSE-X86-GISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-X86-GISEL-NEXT: movl $128100944, %ecx # imm = 0x7A2AA50
; SSE-X86-GISEL-NEXT: movl %ecx, (%eax)
; SSE-X86-GISEL-NEXT: movl $-632258670, %ecx # imm = 0xDA507F92
; SSE-X86-GISEL-NEXT: movl %ecx, 4(%eax)
; SSE-X86-GISEL-NEXT: movl $-408980432, %ecx # imm = 0xE79F7430
; SSE-X86-GISEL-NEXT: movl %ecx, 8(%eax)
; SSE-X86-GISEL-NEXT: movl $708630551, %ecx # imm = 0x2A3CD817
; SSE-X86-GISEL-NEXT: movl %ecx, 12(%eax)
; SSE-X86-GISEL-NEXT: movl $-871899055, %ecx # imm = 0xCC07E051
; SSE-X86-GISEL-NEXT: movl %ecx, 16(%eax)
; SSE-X86-GISEL-NEXT: movl $-633489957, %ecx # imm = 0xDA3DB5DB
; SSE-X86-GISEL-NEXT: movl %ecx, 20(%eax)
; SSE-X86-GISEL-NEXT: movl $591019567, %ecx # imm = 0x233A3E2F
; SSE-X86-GISEL-NEXT: movl %ecx, 24(%eax)
; SSE-X86-GISEL-NEXT: movl $708632899, %ecx # imm = 0x2A3CE143
; SSE-X86-GISEL-NEXT: movl %ecx, 28(%eax)
; SSE-X86-GISEL-NEXT: movl $128100944, (%eax) # imm = 0x7A2AA50
; SSE-X86-GISEL-NEXT: movl $-632258670, 4(%eax) # imm = 0xDA507F92
; SSE-X86-GISEL-NEXT: movl $-408980432, 8(%eax) # imm = 0xE79F7430
; SSE-X86-GISEL-NEXT: movl $708630551, 12(%eax) # imm = 0x2A3CD817
; SSE-X86-GISEL-NEXT: movl $-871899055, 16(%eax) # imm = 0xCC07E051
; SSE-X86-GISEL-NEXT: movl $-633489957, 20(%eax) # imm = 0xDA3DB5DB
; SSE-X86-GISEL-NEXT: movl $591019567, 24(%eax) # imm = 0x233A3E2F
; SSE-X86-GISEL-NEXT: movl $708632899, 28(%eax) # imm = 0x2A3CE143
; SSE-X86-GISEL-NEXT: retl
ret <8 x i32> <i32 128100944, i32 3662708626, i32 3885986864, i32 708630551, i32 -871899055, i32 3661477339, i32 4885986863, i32 708632899>
}

21
llvm/test/CodeGen/X86/isel-buildvector-sse2.ll
View File

@ -20,20 +20,13 @@ define <7 x i8> @test_vector_v7i8() {
; SSE2-GISEL-LABEL: test_vector_v7i8:
; SSE2-GISEL: # %bb.0:
; SSE2-GISEL-NEXT: movq %rdi, %rax
; SSE2-GISEL-NEXT: movb $4, %cl
; SSE2-GISEL-NEXT: movb $8, %dl
; SSE2-GISEL-NEXT: movb $15, %sil
; SSE2-GISEL-NEXT: movb $16, %dil
; SSE2-GISEL-NEXT: movb $23, %r8b
; SSE2-GISEL-NEXT: movb $42, %r9b
; SSE2-GISEL-NEXT: movb $63, %r10b
; SSE2-GISEL-NEXT: movb %cl, (%rax)
; SSE2-GISEL-NEXT: movb %dl, 1(%rax)
; SSE2-GISEL-NEXT: movb %sil, 2(%rax)
; SSE2-GISEL-NEXT: movb %dil, 3(%rax)
; SSE2-GISEL-NEXT: movb %r8b, 4(%rax)
; SSE2-GISEL-NEXT: movb %r9b, 5(%rax)
; SSE2-GISEL-NEXT: movb %r10b, 6(%rax)
; SSE2-GISEL-NEXT: movb $4, (%rdi)
; SSE2-GISEL-NEXT: movb $8, 1(%rdi)
; SSE2-GISEL-NEXT: movb $15, 2(%rdi)
; SSE2-GISEL-NEXT: movb $16, 3(%rdi)
; SSE2-GISEL-NEXT: movb $23, 4(%rdi)
; SSE2-GISEL-NEXT: movb $42, 5(%rdi)
; SSE2-GISEL-NEXT: movb $63, 6(%rdi)
; SSE2-GISEL-NEXT: retq
ret <7 x i8> <i8 4, i8 8, i8 15, i8 16, i8 23, i8 42, i8 63>
}

8
llvm/test/CodeGen/X86/isel-icmp.ll
View File

@ -50,8 +50,8 @@ define i32 @test_icmp_eq_i8(i8 %a, i8 %b) {
;
; GISEL-X86-LABEL: test_icmp_eq_i8:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl %eax, %eax
; GISEL-X86-NEXT: cmpb %dl, %cl
; GISEL-X86-NEXT: sete %al
@ -105,8 +105,8 @@ define i32 @test_icmp_eq_i16(i16 %a, i16 %b) {
;
; GISEL-X86-LABEL: test_icmp_eq_i16:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl %eax, %eax
; GISEL-X86-NEXT: cmpw %dx, %cx
; GISEL-X86-NEXT: sete %al

80
llvm/test/CodeGen/X86/isel-or.ll
View File

@ -21,8 +21,8 @@ define i1 @or_i1(i1 %a, i1 %b) {
;
; GISEL-X86-LABEL: or_i1:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -66,8 +66,8 @@ define i8 @or_i8(i8 %a, i8 %b) {
;
; GISEL-X86-LABEL: or_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -111,8 +111,8 @@ define i16 @or_i16(i16 %a, i16 %b) {
;
; GISEL-X86-LABEL: or_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orw %cx, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -230,7 +230,7 @@ define i8 @or_imm8_i8(i8 %a) {
;
; GISEL-X86-LABEL: or_imm8_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orb $1, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -261,7 +261,7 @@ define i16 @or_imm8_i16(i16 %a) {
;
; GISEL-X86-LABEL: or_imm8_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orw $6, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -291,11 +291,23 @@ define i16 @or_imm8_i16(i16 %a) {
}
define i32 @or_imm8_i32(i32 %a) {
; X86-LABEL: or_imm8_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl $-5, %eax
; X86-NEXT: retl
; SDAG-X86-LABEL: or_imm8_i32:
; SDAG-X86: # %bb.0:
; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; SDAG-X86-NEXT: orl $-5, %eax
; SDAG-X86-NEXT: retl
;
; FASTISEL-X86-LABEL: or_imm8_i32:
; FASTISEL-X86: # %bb.0:
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: orl $-5, %eax
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: or_imm8_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-5, %eax
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm8_i32:
; X64: # %bb.0:
@ -323,10 +335,10 @@ define i64 @or_imm8_i64(i64 %a) {
;
; GISEL-X86-LABEL: or_imm8_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: orl $1, %eax
; GISEL-X86-NEXT: orl $0, %edx
; GISEL-X86-NEXT: movl $1, %eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm8_i64:
@ -354,7 +366,7 @@ define i16 @or_imm16_i16(i16 %a) {
;
; GISEL-X86-LABEL: or_imm16_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orw $1023, %ax # imm = 0x3FF
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -398,8 +410,8 @@ define i32 @or_imm16_i32(i32 %a) {
;
; GISEL-X86-LABEL: or_imm16_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: movl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm16_i32:
@ -428,10 +440,10 @@ define i64 @or_imm16_i64(i64 %a) {
;
; GISEL-X86-LABEL: or_imm16_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: orl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: orl $-1, %edx
; GISEL-X86-NEXT: movl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm16_i64:
@ -458,8 +470,8 @@ define i32 @or_imm32_i32(i32 %a) {
;
; GISEL-X86-LABEL: or_imm32_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: movl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm32_i32:
@ -488,10 +500,10 @@ define i64 @or_imm32_i64(i64 %a) {
;
; GISEL-X86-LABEL: or_imm32_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: orl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: orl $-1, %edx
; GISEL-X86-NEXT: movl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm32_i64:
@ -522,10 +534,10 @@ define i64 @or_imm64_i64(i64 %a) {
;
; GISEL-X86-LABEL: or_imm64_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: orl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: orl $-2, %edx
; GISEL-X86-NEXT: movl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: movl $-2, %edx
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: or_imm64_i64:

6
llvm/test/CodeGen/X86/isel-phi.ll
View File

@ -364,9 +364,9 @@ define ptr @test_ptr(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, i1
; GLOBAL-X64-LABEL: test_ptr:
; GLOBAL-X64: # %bb.0: # %entry
; GLOBAL-X64-NEXT: movq %rdi, %rax
; GLOBAL-X64-NEXT: movl {{[0-9]+}}(%rsp), %r11d
; GLOBAL-X64-NEXT: movl {{[0-9]+}}(%rsp), %r10d
; GLOBAL-X64-NEXT: movl {{[0-9]+}}(%rsp), %edi
; GLOBAL-X64-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
; GLOBAL-X64-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
; GLOBAL-X64-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
; GLOBAL-X64-NEXT: testb $1, %r11b
; GLOBAL-X64-NEXT: je .LBB7_4
; GLOBAL-X64-NEXT: # %bb.1: # %cond.true

8
llvm/test/CodeGen/X86/isel-sdiv.ll
View File

@ -21,9 +21,9 @@ define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_sdiv_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: cbtw
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: idivb %cl
; GISEL-X86-NEXT: retl
%ret = sdiv i8 %arg1, %arg2
@ -48,8 +48,8 @@ define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_sdiv_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: cwtd
; GISEL-X86-NEXT: idivw %cx

40
llvm/test/CodeGen/X86/isel-select-cmov.ll
View File

@ -95,23 +95,23 @@ define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b
;
; GISEL-X86-LABEL: select_cmov_i8:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: testl %eax, %eax
; GISEL-X86-NEXT: je LBB0_1
; GISEL-X86-NEXT: ## %bb.2:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: ## kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
; GISEL-X86-NEXT: LBB0_1:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: ## kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
;
; GISEL-X86-CMOV-LABEL: select_cmov_i8:
; GISEL-X86-CMOV: ## %bb.0:
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: testl %ecx, %ecx
; GISEL-X86-CMOV-NEXT: cmovnew %dx, %ax
; GISEL-X86-CMOV-NEXT: ## kill: def $al killed $al killed $eax
@ -198,23 +198,23 @@ define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroex
;
; GISEL-X86-LABEL: select_cmov_i16:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: testl %eax, %eax
; GISEL-X86-NEXT: je LBB1_1
; GISEL-X86-NEXT: ## %bb.2:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: ## kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
; GISEL-X86-NEXT: LBB1_1:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: ## kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
;
; GISEL-X86-CMOV-LABEL: select_cmov_i16:
; GISEL-X86-CMOV: ## %bb.0:
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movzwl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: testl %ecx, %ecx
; GISEL-X86-CMOV-NEXT: cmovnew %dx, %ax
; GISEL-X86-CMOV-NEXT: ## kill: def $ax killed $ax killed $eax
@ -300,8 +300,8 @@ define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
;
; GISEL-X86-LABEL: select_cmp_cmov_i16:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: cmpw %ax, %cx
; GISEL-X86-NEXT: setb %dl
@ -315,8 +315,8 @@ define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
;
; GISEL-X86-CMOV-LABEL: select_cmp_cmov_i16:
; GISEL-X86-CMOV: ## %bb.0:
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: xorl %edx, %edx
; GISEL-X86-CMOV-NEXT: cmpw %cx, %ax
; GISEL-X86-CMOV-NEXT: setb %dl
@ -400,7 +400,7 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
;
; GISEL-X86-LABEL: select_cmov_i32:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: testl %eax, %eax
; GISEL-X86-NEXT: je LBB3_1
; GISEL-X86-NEXT: ## %bb.2:
@ -412,7 +412,7 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
;
; GISEL-X86-CMOV-LABEL: select_cmov_i32:
; GISEL-X86-CMOV: ## %bb.0:
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: testl %ecx, %ecx
; GISEL-X86-CMOV-NEXT: cmovnel {{[0-9]+}}(%esp), %eax
@ -595,7 +595,7 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
;
; GISEL-X86-LABEL: select_cmov_i64:
; GISEL-X86: ## %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: testl %ecx, %ecx
; GISEL-X86-NEXT: je LBB5_1
; GISEL-X86-NEXT: ## %bb.2:
@ -615,7 +615,7 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
;
; GISEL-X86-CMOV-LABEL: select_cmov_i64:
; GISEL-X86-CMOV: ## %bb.0:
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-CMOV-NEXT: testl %ecx, %ecx

8
llvm/test/CodeGen/X86/isel-srem.ll
View File

@ -48,9 +48,9 @@ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_srem_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: cbtw
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: idivb %cl
; GISEL-X86-NEXT: movb %ah, %al
; GISEL-X86-NEXT: retl
@ -78,8 +78,8 @@ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_srem_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: cwtd
; GISEL-X86-NEXT: idivw %cx

3
llvm/test/CodeGen/X86/isel-traps.ll
View File

@ -63,8 +63,7 @@ define void @test_ubsantrap_custom() nounwind {
; GISEL-X86-LABEL: test_ubsantrap_custom:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: subl $12, %esp
; GISEL-X86-NEXT: movl $42, %eax
; GISEL-X86-NEXT: movl %eax, (%esp)
; GISEL-X86-NEXT: movl $42, (%esp)
; GISEL-X86-NEXT: calll guide
; GISEL-X86-NEXT: addl $12, %esp
; GISEL-X86-NEXT: retl

8
llvm/test/CodeGen/X86/isel-udiv.ll
View File

@ -21,9 +21,9 @@ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_udiv_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl %al, %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: divb %cl
; GISEL-X86-NEXT: retl
%ret = udiv i8 %arg1, %arg2
@ -48,8 +48,8 @@ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_udiv_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: divw %cx

8
llvm/test/CodeGen/X86/isel-urem.ll
View File

@ -48,9 +48,9 @@ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_urem_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl %al, %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: divb %cl
; GISEL-X86-NEXT: movb %ah, %al
; GISEL-X86-NEXT: retl
@ -78,8 +78,8 @@ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) nounwind {
;
; GISEL-X86-LABEL: test_urem_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: divw %cx

6
llvm/test/CodeGen/X86/isel-x87.ll
View File

@ -186,8 +186,7 @@ define void @f6(ptr %a, ptr %b) nounwind {
; GISEL_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL_X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL_X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; GISEL_X86-NEXT: flds (%eax)
; GISEL_X86-NEXT: faddp %st, %st(1)
; GISEL_X86-NEXT: fadds (%eax)
; GISEL_X86-NEXT: fstps (%ecx)
; GISEL_X86-NEXT: retl
;
@ -203,8 +202,7 @@ define void @f6(ptr %a, ptr %b) nounwind {
; GISEL_X64-LABEL: f6:
; GISEL_X64: # %bb.0:
; GISEL_X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; GISEL_X64-NEXT: flds (%rdi)
; GISEL_X64-NEXT: faddp %st, %st(1)
; GISEL_X64-NEXT: fadds (%rdi)
; GISEL_X64-NEXT: fstps (%rsi)
; GISEL_X64-NEXT: retq
;

80
llvm/test/CodeGen/X86/isel-xor.ll
View File

@ -21,8 +21,8 @@ define i1 @xor_i1(i1 %a, i1 %b) {
;
; GISEL-X86-LABEL: xor_i1:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -66,8 +66,8 @@ define i8 @xor_i8(i8 %a, i8 %b) {
;
; GISEL-X86-LABEL: xor_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorb %cl, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -111,8 +111,8 @@ define i16 @xor_i16(i16 %a, i16 %b) {
;
; GISEL-X86-LABEL: xor_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorw %cx, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -230,7 +230,7 @@ define i8 @xor_imm8_i8(i8 %a) {
;
; GISEL-X86-LABEL: xor_imm8_i8:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorb $1, %al
; GISEL-X86-NEXT: # kill: def $al killed $al killed $eax
; GISEL-X86-NEXT: retl
@ -261,7 +261,7 @@ define i16 @xor_imm8_i16(i16 %a) {
;
; GISEL-X86-LABEL: xor_imm8_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorw $6, %ax
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -291,11 +291,23 @@ define i16 @xor_imm8_i16(i16 %a) {
}
define i32 @xor_imm8_i32(i32 %a) {
; X86-LABEL: xor_imm8_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: xorl $-5, %eax
; X86-NEXT: retl
; SDAG-X86-LABEL: xor_imm8_i32:
; SDAG-X86: # %bb.0:
; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; SDAG-X86-NEXT: xorl $-5, %eax
; SDAG-X86-NEXT: retl
;
; FASTISEL-X86-LABEL: xor_imm8_i32:
; FASTISEL-X86: # %bb.0:
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: xorl $-5, %eax
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: xor_imm8_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-5, %eax
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm8_i32:
; X64: # %bb.0:
@ -323,10 +335,10 @@ define i64 @xor_imm8_i64(i64 %a) {
;
; GISEL-X86-LABEL: xor_imm8_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl $1, %eax
; GISEL-X86-NEXT: xorl $0, %edx
; GISEL-X86-NEXT: movl $1, %eax
; GISEL-X86-NEXT: xorl %edx, %edx
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm8_i64:
@ -354,7 +366,7 @@ define i16 @xor_imm16_i16(i16 %a) {
;
; GISEL-X86-LABEL: xor_imm16_i16:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorw $1023, %ax # imm = 0x3FF
; GISEL-X86-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-X86-NEXT: retl
@ -398,8 +410,8 @@ define i32 @xor_imm16_i32(i32 %a) {
;
; GISEL-X86-LABEL: xor_imm16_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: movl $2044, %eax # imm = 0x7FC
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm16_i32:
@ -430,10 +442,10 @@ define i64 @xor_imm16_i64(i64 %a) {
;
; GISEL-X86-LABEL: xor_imm16_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: notl %edx
; GISEL-X86-NEXT: movl $-5022, %eax # imm = 0xEC62
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm16_i64:
@ -460,8 +472,8 @@ define i32 @xor_imm32_i32(i32 %a) {
;
; GISEL-X86-LABEL: xor_imm32_i32:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: movl $85538, %eax # imm = 0x14E22
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm32_i32:
@ -492,10 +504,10 @@ define i64 @xor_imm32_i64(i64 %a) {
;
; GISEL-X86-LABEL: xor_imm32_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: notl %edx
; GISEL-X86-NEXT: movl $-125778, %eax # imm = 0xFFFE14AE
; GISEL-X86-NEXT: movl $-1, %edx
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm32_i64:
@ -526,10 +538,10 @@ define i64 @xor_imm64_i64(i64 %a) {
;
; GISEL-X86-LABEL: xor_imm64_i64:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: xorl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: xorl $-2, %edx
; GISEL-X86-NEXT: movl $-1850691612, %eax # imm = 0x91B0AFE4
; GISEL-X86-NEXT: movl $-2, %edx
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
;
; X64-LABEL: xor_imm64_i64: