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[AMDGPU] Make use of SIInstrInfo::isWaitcnt. NFC. (#154087)

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This commit is contained in:
Jay Foad 2025-08-18 16:18:46 +01:00 committed by GitHub
parent 6ce13ae1c2
commit f15c6ff6cb
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GPG Key ID: B5690EEEBB952194
2 changed files with 5 additions and 33 deletions
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36
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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@ -1357,17 +1357,10 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
// DsCnt corresponds to LGKMCnt here.
return (Decoded.DsCnt == 0);
}
case AMDGPU::S_WAIT_STORECNT:
case AMDGPU::S_WAIT_STORECNT_DSCNT:
case AMDGPU::S_WAIT_LOADCNT:
case AMDGPU::S_WAIT_LOADCNT_DSCNT:
case AMDGPU::S_WAIT_SAMPLECNT:
case AMDGPU::S_WAIT_BVHCNT:
case AMDGPU::S_WAIT_DSCNT:
case AMDGPU::S_WAIT_EXPCNT:
case AMDGPU::S_WAIT_KMCNT:
llvm_unreachable("unexpected wait count instruction");
default:
assert((!SIInstrInfo::isWaitcnt(MI.getOpcode()) ||
MI.getOpcode() == AMDGPU::S_WAIT_IDLE) &&
"unexpected wait count instruction");
// SOPP instructions cannot mitigate the hazard.
if (TII->isSOPP(MI))
return false;
@ -2257,28 +2250,7 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
if (WaitStates >= 3 || SIInstrInfo::isVALU(MI))
return true;
switch (MI.getOpcode()) {
case AMDGPU::S_WAITCNT:
case AMDGPU::S_WAITCNT_VSCNT:
case AMDGPU::S_WAITCNT_VMCNT:
case AMDGPU::S_WAITCNT_EXPCNT:
case AMDGPU::S_WAITCNT_LGKMCNT:
case AMDGPU::S_WAIT_IDLE:
case AMDGPU::S_WAIT_LOADCNT:
case AMDGPU::S_WAIT_LOADCNT_DSCNT:
case AMDGPU::S_WAIT_SAMPLECNT:
case AMDGPU::S_WAIT_BVHCNT:
case AMDGPU::S_WAIT_STORECNT:
case AMDGPU::S_WAIT_STORECNT_DSCNT:
case AMDGPU::S_WAIT_EXPCNT:
case AMDGPU::S_WAIT_DSCNT:
case AMDGPU::S_WAIT_KMCNT:
return true;
default:
break;
}
return false;
return SIInstrInfo::isWaitcnt(MI.getOpcode());
};
return FPAtomicToDenormModeWaitStates -

2
llvm/lib/Target/AMDGPU/SIInstrInfo.h
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@ -1056,7 +1056,7 @@ public:
}
}
bool isWaitcnt(unsigned Opcode) const {
static bool isWaitcnt(unsigned Opcode) {
switch (getNonSoftWaitcntOpcode(Opcode)) {
case AMDGPU::S_WAITCNT:
case AMDGPU::S_WAITCNT_VSCNT: