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[X86] canCreateUndefOrPoisonForTargetNode - SSE vector shifts handle out of bounds shift amounts

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SHL/SRL are guaranteed to fold to zero, SRA is guaranteed to fold to 'all sign bits'
This commit is contained in:
Simon Pilgrim 2024-05-24 12:45:34 +01:00
parent 2171f34121
commit fcd086ca27
2 changed files with 7 additions and 6 deletions
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7
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -42930,7 +42930,6 @@ bool X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(
bool PoisonOnly, unsigned Depth) const {
unsigned NumElts = DemandedElts.getBitWidth();
// TODO: Add more target shuffles.
switch (Op.getOpcode()) {
case X86ISD::PSHUFD:
case X86ISD::VPERMILPI: {
@ -42966,8 +42965,12 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode(
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
// TODO: Add more target shuffles.
switch (Op.getOpcode()) {
// SSE vector shifts handle out of bounds shift amounts.
case X86ISD::VSHLI:
case X86ISD::VSRLI:
case X86ISD::VSRAI:
return false;
case X86ISD::PSHUFD:
case X86ISD::VPERMILPI:
case X86ISD::UNPCKH:

6
llvm/test/CodeGen/X86/freeze-binary.ll
View File

@ -546,9 +546,8 @@ define <8 x i16> @freeze_ashr_vec(<8 x i16> %a0) nounwind {
define <4 x i32> @freeze_ashr_vec_outofrange(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_ashr_vec_outofrange:
; X86: # %bb.0:
; X86-NEXT: psrad $1, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
; X86-NEXT: psrad $2, %xmm0
; X86-NEXT: psrad $3, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr_vec_outofrange:
@ -660,9 +659,8 @@ define <8 x i16> @freeze_lshr_vec(<8 x i16> %a0) nounwind {
define <4 x i32> @freeze_lshr_vec_outofrange(<4 x i32> %a0) nounwind {
; X86-LABEL: freeze_lshr_vec_outofrange:
; X86: # %bb.0:
; X86-NEXT: psrld $1, %xmm0
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
; X86-NEXT: psrld $2, %xmm0
; X86-NEXT: psrld $3, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: freeze_lshr_vec_outofrange: