548919 Commits

Author SHA1 Message Date
Tim Gymnich
ffaba758fb
[MLIR][ROCDL] Add permlane16.swap and permanlane32.swap (#153804)
add rocdl.permlane16.swap and rocdl.permanlane32.swap
2025-08-15 17:35:31 +02:00
Simon Pilgrim
38eb14f27c [X86] avx512vbmi2-builtins.c / avx512vlvbmi2-builtins.c - add C/C++ and 32/64-bit test coverage 2025-08-15 16:35:16 +01:00
Simon Pilgrim
7df862818e [X86] avx512vbmi-builtins.c / avx512vbmivl-builtin.c - add C/C++ and 32/64-bit test coverage 2025-08-15 16:35:15 +01:00
Tim Renouf
f279c47cb3
AMDGPU gfx12: Add _dvgpr$ symbols for dynamic VGPRs (#148251)
For each function with the AMDGPU_CS_Chain calling convention, with
dynamic VGPRs enabled, add a _dvgpr$ symbol, with the value of the
function symbol, plus an offset encoding one less than the number of
VGPR blocks used by the function (16 VGPRs per block, no more than 128)
in bits 5..3 of the symbol value. This is used by a front-end to have
functions that are chained rather than called, and a dispatcher that
dynamically resizes the VGPR count before dispatching to a function.
2025-08-15 16:33:06 +01:00
Aiden Grossman
0b04168948
[CI] Add Basic Bazel Checks (#153740)
Having basic checks (like running buildifier) on the upstream bazel
files would be helpful for contributors maintaining the bazel build. Add
basic checks (currently just buildifier) to a workflow that runs
whenever the bazel build files change.
2025-08-15 08:30:07 -07:00
cmtice
6d3ad9d9fd
[LLDB] Update DIL handling of array subscripting. (#151605)
This updates the DIL code for handling array subscripting to more
closely match and handle all the cases from the original 'frame var'
implementation. Also updates the DIL array subscripting test. This
particularly fixes some issues with handling synthetic children, objc
pointers, and accessing specific bits within scalar data types.
2025-08-15 08:26:45 -07:00
Nikita Popov
11c2240049 [SDAGBuilder] Rename RetTys -> RetVTs (NFC)
Make it clearer that this is a vector of EVTs, not IR types.

Based on:
https://github.com/llvm/llvm-project/pull/153798#discussion_r2279066696
2025-08-15 17:06:33 +02:00
Philip Reames
606937474e
[SDAG] Remove IndexType manipulation in getUniformBase and callers (#151578)
All paths set it to the same value, just propagate that value to the
consumer.
2025-08-15 08:00:47 -07:00
Florian Hahn
2b1e06598f
[LV] Regenerate some more check lines. (NFC) 2025-08-15 15:53:19 +01:00
Alexey Bataev
13b54f7dc1 [SLP] Recalculate dependencies for potential control dependencies if cleared
If the control dependecies are cleared after calcellation of the
copyables, need to reclculate them unconditionally.

Fixes #153754 #153676
2025-08-15 07:52:10 -07:00
Phoebe Wang
f24d91eb2c
[Headers][X86] Remove duplicate __v8hu, NFCI (#153734)
Newly added in xmmintrin.h by c8312bdd1665225c585dd2b0bff5e46d569edd45
2025-08-15 22:48:59 +08:00
David Green
144f3c4cbf
[AArch64] Adjust the scheduling info of SVE FCMP on Cortex-A510. (#153810)
According to the SWOG, these have a lower throughput than other
instructions. Mark them as taking multiple cycles to model that.
2025-08-15 15:45:33 +01:00
Mikhail R. Gadelha
d7199544af
[libc] Fix mbrtowc test (#153721)
Previously, we were trying to memset a pointer that wasn't being
initialized, and the test would randomly fail.

This PR replaces the pointers with actual objects.
2025-08-15 11:44:33 -03:00
Akash Banerjee
1fd1d63463 [MLIR][OpenMP] Add a new AutomapToTargetData conversion pass in FIR (#153048)
Add a new AutomapToTargetData pass. This gathers the declare target
enter variables which have the AUTOMAP modifier. And adds
omp.declare_target_enter/exit mapping directives for fir.alloca and
fir.free oeprations on the AUTOMAP enabled variables.

Automap Ref: OpenMP 6.0 section 7.9.7.
2025-08-15 15:41:41 +01:00
Simon Pilgrim
09267f6720 [X86] avx512vp2intersect-builtins.c / avx512vlvp2intersect-builtins.c - add C/C++ and 32/64-bit test coverage 2025-08-15 15:39:12 +01:00
Krishna Pandey
6602d6c7a7
[libc][math][docs] Add documentation for BFloat16 type (#153475)
Signed-off-by: Krishna Pandey <kpandey81930@gmail.com>
2025-08-15 20:07:33 +05:30
Matt Arsenault
9a14b1d254
RuntimeLibcalls: Generate table of libcall name lengths (#153210)
Avoids strlen when constructing the returned StringRef. We were emitting
these in the libcall name lookup anyway, so split out the offsets for
general use.

Currently emitted as a separate table, not sure if it would be better
to change the string offset table to store pairs of offset and width
instead.
2025-08-15 23:29:10 +09:00
Benjamin Chetioui
8c0914d826
[mlir][bazel] Fix Bazel build after 6bb8f6f2d0ed672217e0a0521afc5b86913b717e (#153811) 2025-08-15 14:28:44 +00:00
Kazu Hirata
f4bc3151bb [mlir] Fix warnings
This patch fixes:

  mlir/lib/Target/Wasm/TranslateFromWasm.cpp:82:1: error: unused
  variable 'wasmSectionName<(anonymous
  namespace)::WasmSectionType::DATACOUNT>'
  [-Werror,-Wunused-const-variable]

  mlir/lib/Target/Wasm/TranslateFromWasm.cpp💯5: error: unused
  variable 'valueTypesEncodings' [-Werror,-Wunused-const-variable]

  mlir/lib/Target/Wasm/TranslateFromWasm.cpp:735:13: error: unused
  function 'buildLiteralType<unsigned int>'
  [-Werror,-Wunused-function]

  mlir/lib/Target/Wasm/TranslateFromWasm.cpp:740:13: error: unused
  function 'buildLiteralType<unsigned long>'
  [-Werror,-Wunused-function]

  mlir/lib/Target/Wasm/TranslateFromWasm.cpp:292:33: error: private
  field 'symbols' is not used [-Werror,-Wunused-private-field]
2025-08-15 07:24:31 -07:00
Simon Pilgrim
17dd57b00e [X86] avxvnni-builtins.c / avxvnniint8-builtins.c / avxvnniint16-builtins.c - add C/C++ and 32/64-bit test coverage 2025-08-15 15:17:15 +01:00
Guray Ozen
4c389178ee
[MLIR][NVVM] Print readable modifer (NFC) (#153779)
Currently, modifier is printed as address, so it is not readable and not
useful. This PR adds readable printing for it.

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
2025-08-15 15:47:39 +02:00
Guray Ozen
af92cabdef
[MLIR][NVVM] Combine griddepcontrol Ops (#152525)
We've 2 ops:
1. nvvm.griddepcontrol.wait
2. nvvm.griddepcontrol.launch_dependents

They are related to Grid Dependent Launch (or programmatic dependent
launch in CUDA) and same concept. This PR unifies both ops into a single
one.
2025-08-15 15:47:12 +02:00
Erich Keane
15d7a95ea9
[CIR] Refactor recipe init generation, cleanup after init (#153610)
In preperation of the firstprivate implementation, this separates out
some functions to make it easier to read.

Additionally, it cleans up the VarDecl->alloca relationship, which will
prevent issues if we have to re-use the same vardecl for a future
generated recipe (and causes concerns in firstprivate later).
2025-08-15 06:41:42 -07:00
Gaëtan Bossu
9828745661
[AArch64][ISel] Select constructive EXT_ZZI pseudo instruction (#152554)
The patch adds patterns to select the EXT_ZZI_CONSTRUCTIVE pseudo
instead of the EXT_ZZI destructive instruction for vector_splice. This
only works when the two inputs to vector_splice are identical.

Given that registers aren't tied anymore, this gives the register
allocator more freedom and a lot of MOVs get replaced with MOVPRFX.

In some cases however, we could have just chosen the same input and
output register, but regalloc preferred not to. This means we end up
with some test cases now having more instructions: there is now a
MOVPRFX while no MOV was previously needed.
2025-08-15 14:30:24 +01:00
David Green
649762cb04 Revert "[AArch64][GlobalISel] Add additional vecreduce.fadd and fadd 0.0 tests. NFC"
This reverts commit 16314eb7312dab38d721c70f247f2117e9800704 as the test cases
are failing under EXPENSIVE_CHECKS. Scalar vecreduce.fadd are not valid in
GISel.
2025-08-15 14:23:53 +01:00
Stephen Tozer
bc216b057d
[Debugify] Improve reduction of debugify coverage build output (#150212)
In current DebugLoc coverage builds, the output for any reasonably large
build can become very large if any missing DebugLocs are present; this
happens because single errors in LLVM may result in many errors being
reported in the output report. The main cause of this is that the empty
locations attached to instructions may be propagated to other
instructions in later passes, which will each be reported as new errors.
This patch prevents this by adding an "unknown" annotation to
instructions after reporting them once, ensuring that any other
DebugLocs copied or derived from the original empty location will not be
marked as new errors.

As a separate but related change, this patch updates the report
generation script to deduplicate results using the recorded stacktrace
if they are available, instead of the pass+instruction combination. This
reduces the size of the reduction, but makes the reduction highly
reliable, as the stacktrace allows us to very precisely identify when
two bugs have originated from the same place.
2025-08-15 14:01:04 +01:00
Simon Pilgrim
bcb4984a0b [X86] select-smin-smax.ll - add i128 tests
Helps check quality of legality codegen (all we had was x86 i64 handling)
2025-08-15 13:48:13 +01:00
Simon Pilgrim
263e458273
[X86] select-smin-smax.ll - add i8/i16 test coverage (#153788)
Pulled out of #151893 to show 32/64-bit target coverage
2025-08-15 13:37:11 +01:00
Erick Ochoa Lopez
61caab7789
[mlir][llvm] Add align attribute to llvm.intr.masked.{expandload,compressstore} (#153063)
* Add `requiresArgsAndResultsAttr` to `LLVM_OneResultIntrOp`
* Add `args_attrs` to `llvm.intr.masked.{expandload,compressstore}`

The LLVM intrinsics
[`llvm.intr.masked.expandload`](https://llvm.org/docs/LangRef.html#llvm-masked-expandload-intrinsics)
and
[`llvm.intr.masked.compressstore`](https://llvm.org/docs/LangRef.html#llvm-masked-compressstore-intrinsics)
both allow an optional align parameter attribute to be set which
defaults to one.

Inlining the documentation below for [`llvm.intr.masked.expandload` 's
](https://llvm.org/docs/LangRef.html#id1522) and
[`llvm.intr.masked.compressstore`'s](https://llvm.org/docs/LangRef.html#id1522)
arguments respectively

> The `align` parameter attribute can be provided for the first
argument. The pointer alignment defaults to 1.

> The `align` parameter attribute can be provided for the second
argument. The pointer alignment defaults to 1.
2025-08-15 08:34:14 -04:00
Mehdi Amini
69453d7021
[MLIR] Fix memory leak in importWebAssemblyToModule when it fails to import (#153794) 2025-08-15 12:33:25 +00:00
David Spickett
0fca1e4e06 [lldb][lldb-dap][test] Correct skip in TestDAP_launch
Fixes 4f65345ab5f2787a4704efb5828657c50be6d65a

Yet again I forgot it's skip[I]f.
2025-08-15 12:29:26 +00:00
Mehdi Amini
7640645f79
[MLIR][Wasm] Remove statistics as they depend on global ctors (#153795)
Use a debug log instead for now.
2025-08-15 12:29:20 +00:00
David Spickett
4f65345ab5 [lldb][lldb-dap][test] Disable part of TestDAP_launch on Arm 32-bit
This test has been flakey on our bot:
https://lab.llvm.org/buildbot/#/builders/18/builds/20410

```
======================================================================
FAIL: test_extra_launch_commands (TestDAP_launch.TestDAP_launch)
    Tests the "launchCommands" with extra launching settings
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tcwg-buildbot/worker/lldb-arm-ubuntu/llvm-project/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py", line 482, in test_extra_launch_commands
    self.verify_commands("stopCommands", output, stopCommands)
  File "/home/tcwg-buildbot/worker/lldb-arm-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py", line 228, in verify_commands
    self.assertTrue(
AssertionError: False is not true : verify 'frame variable' found in console output for 'stopCommands'
Config=arm-/home/tcwg-buildbot/worker/lldb-arm-ubuntu/build/bin/clang
----------------------------------------------------------------------
```

Likely a timing issue waiting for the command output on a slower
machine.

General tracking issue - https://github.com/llvm/llvm-project/issues/137660
2025-08-15 12:26:45 +00:00
Gaëtan Bossu
69e105beec
[AArch64][ISel] Add unary vector_splice tests (NFC) (#152553)
They use extract shuffles for fixed vectors, and
llvm.vector.splice intrinsics for scalable vectors.

In the previous tests using ld+extract+st, the extract was optimized
away and replaced by a smaller load at the right offset. This meant
we didn't really test the vector_splice ISD node.
2025-08-15 13:15:35 +01:00
⭐️NINIKA⭐️
ce0bc3aa70 [lldb][docs] document an analogue for info proc mappings (#153559) 2025-08-15 12:01:52 +00:00
Simon Pilgrim
6ad39bc866 [X86] avxifma-builtins.c / avx512ifma-builtins.c / avx512ifmavl-builtins.c - add C/C++ and 32/64-bit test coverage 2025-08-15 12:09:54 +01:00
Simon Pilgrim
a9ff15d893
[X86] select-smin-smax.ll - add 32-bit test coverage (#153780)
Inspired by #151893
2025-08-15 12:05:41 +01:00
Tobias Stadler
d803a93f55
[Inliner] Report inlining decision before deleting Callee contents (#153616)
Call `recordInliningWithCalleeDeleted` before dropping the contents of
the Callee. Otherwise the handlers don't have access to e.g. the
DebugLoc, so the Callee DebugLoc was missing in inlining remarks for
functions with internal linkage.

The test is the same as `optimization-remarks-passed-yaml.ll` except
that the function `foo` has internal linkage instead of external linkage.
2025-08-15 12:00:34 +01:00
Yanzuo Liu
3b27d50cc7
[LLVM][utils] Add script which clears release notes (#153593)
The script copies `ReleaseNotesTemplate.txt` to corresponding
`ReleaseNotes.rst`/`.md` to clear release notes.

The suffix of `ReleaseNotesTemplate.txt` must be `.txt`. If it is
`.rst`/`.md`, it will be treated as a documentation source file when
building documentation.
2025-08-15 19:00:08 +08:00
Nikita Popov
3db17429da [Mips] Add frexpl and sincosl to f128 libcall list 2025-08-15 12:45:05 +02:00
Pavel Labath
dab971ed23
[llvm-readobj] Dump SFrame relocations as well (#153161)
If there is a relocation for a particular FDE, print it as well. This is
mainly meant for human consumption (otherwise, there's no way to tell
which function a given (relocatable) FDE refers to). For testing of
relocation generation, I'd still recommend using the regular relocation
dumper, as this code will not detect (e.g.) any superfluous relocations.

I've considered handling relocations inside the SFrameParser class, but
I couldn't find an elegant way to do that. Right now, I don't have a use
case for resolving relocations there as lldb (my other use case for
SFrameParser) will always operate on linked objects.
2025-08-15 10:30:41 +00:00
Sergei Barannikov
56681c94f3
[TableGen][DecoderEmitter] Compute bit attribute once (NFC) (#153530)
Pull the logic to compute bit attributes from `filterProcessor()` to its
caller to avoid recomputing them on the second call.
2025-08-15 13:28:38 +03:00
Markus Böck
8582025f1f
[mlir][Transforms] Turn 1:N -> 1:1 dispatch fatal error into match failure (#153605)
Prior to this PR, the default behaviour of a conversion pattern which
receives operands of a 1:N is to abort the compilation. This has
historically been useful when the 1:N type conversion got merged into
the dialect conversion as it allowed us to easily find patterns that
should be capable of handling 1:N type conversions but didn't.

However, this behaviour has the disadvantage of being non-composable:
While the pattern in question cannot handle the 1:N type conversion,
another pattern part of the set might, but doesn't get the chance as
compilation is aborted.

This PR fixes this behaviour by failing to match and instead of
aborting, giving other patterns the chance to legalize an op. The
implementation uses a reusable function called `dispatchTo1To1` to allow
derived conversion patterns to also implement the behaviour.
2025-08-15 11:45:25 +02:00
William Huynh
6b16a276ef
[libc] Add startup code for ARM v7-A, ARM v7-R variants (#153576)
These variants require a different exception table that requires a bit
of initialisation.

This allows us to enable testing for these variants downstream.
2025-08-15 09:17:50 +00:00
Matthias Springer
21b607adbe
[mlir][SCF] scf.for: Add support for unsigned integer comparison (#153379)
Add a new unit attribute to allow for unsigned integer comparison.

Example:
```mlir
scf.for unsigned %iv_32 = %lb_32 to %ub_32 step %step_32 : i32 {
  // body
}
```

Discussion:
https://discourse.llvm.org/t/scf-should-scf-for-support-unsigned-comparison/84655
2025-08-15 10:59:14 +02:00
Ferdinand Lemaire
6bb8f6f2d0
[MLIR][WASM] Introduce an importer for Wasm binaries (#152131)
First step in introducing the wasm-import target to mlir-translate. 
This is the first PR to introduce the pass, with this PR, there is very
little support for the actual WebAssembly language, it's mostly there to
introduce the skeleton of the importer. A follow-up will come with
support for a wider range of operators. It was split to make it easier
to review, since it's a good chunk of work.

---------

Co-authored-by: Luc Forget <dev@alias.lforget.fr>
Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire@woven-planet.global>
Co-authored-by: Jessica Paquette <jessica.paquette@woven-planet.global>
Co-authored-by: Luc Forget <luc.forget@woven.toyota>
2025-08-15 10:54:40 +02:00
Simon Pilgrim
b014d10ed7 [X86] avx512cd-builtins.c + avx512vlcd-builtins.c - add C/C++ and 32/64-bit test coverage 2025-08-15 09:44:18 +01:00
Ross Brunton
30c7951136
[Offload] olLaunchHostFunction (#152482)
Add an `olLaunchHostFunction` method that allows enqueueing host work
to the stream.
2025-08-15 09:39:48 +01:00
Nikita Popov
598562077a [llvm-c] Fix memory leak in test 2025-08-15 10:33:08 +02:00
Florian Hahn
36be0bba2a
[SCEV] Check if predicate is known false for predicated AddRecs. (#151134)
Similarly to https://github.com/llvm/llvm-project/pull/131538, we can
also try and check if a predicate is known to wrap given the backedge
taken count.

For now, this just checks directly when we try to create predicated
AddRecs. This both helps to avoid spending compile-time on optimizations
where we know the predicate is false, and can also help to allow
additional vectorization (e.g. by deciding to scalarize memory accesses
when otherwise we would try to create a predicated AddRec with a
predicate that's always false).

The initial version is quite restricted, but can be extended in
follow-ups to cover more cases.

PR: https://github.com/llvm/llvm-project/pull/151134
2025-08-15 09:30:25 +01:00