107 Commits

Author SHA1 Message Date
Phoebe Wang
99a1d5f7fa
[X86][APX] Remove CF feature from APXF and Diamond Rapids (#153751)
Due to it results in more losses than gains.
2025-08-20 03:07:56 +00:00
Feng Zou
641b2a58ea
[Driver][X86] Add -m[no-]apxf to m_x86_Features_Group (#140874)
This is to expose these options to clang-cl on Windows.
2025-05-26 10:42:53 +08:00
Phoebe Wang
f2987f255a
[X86][AVX10] Make warning message more informative, NFCI (#134528) 2025-04-07 08:31:02 +08:00
Phoebe Wang
c7572ae213
[X86][AVX10] Re-target mavx10.1 and emit warning for mavx10.x-256/512 and m[no-]evex512 (#132542)
The 256-bit maximum vector register size control was removed from AVX10
whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343

- Re-target m[no-]avx10.1 to enable AVX10.1 with 512-bit maximum vector
register size;
- Emit warning for mavx10.x-256, noting AVX10/256 is not supported;
- Emit warning for mavx10.x-512, noting to use m[no-]avx10.x instead;
- Emit warning for m[no-]evex512, noting AVX10/256 is not supported;

This patch only changes Clang driver behavior. The features
avx10.x-256/512 keep unchanged and will be removed in the next release.
2025-03-31 22:05:50 +08:00
Phoebe Wang
9ebfee9d68
[X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511)
Per the feedback we got, we’d like to switch m[no-]avx10.2 to alias of
512 bit options and disable m[no-]avx10.1 due to they were alias of 256
bit options.

We also change -mno-avx10.[1,2]-512 to alias of 256 bit options to
disable both 256 and 512 instructions.
2025-01-30 21:13:49 +08:00
Feng Zou
eddb79d56d
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-11 15:24:18 +08:00
Phoebe Wang
8f4401374c
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
2024-11-09 13:26:10 +08:00
Alan Zhao
ff22515430
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070

Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
2024-11-08 16:15:02 -08:00
Phoebe Wang
58a17e1bbc
[X86][AMX] Support AMX-AVX512 (#114070) 2024-11-08 16:25:16 +08:00
Phoebe Wang
c72a751dab
[X86][AMX] Support AMX-TRANSPOSE (#113532)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-01 16:45:03 +08:00
Freddy Ye
c4248fa3ed
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-25 09:00:19 +08:00
Phoebe Wang
259ca9ee9c
Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-03 09:26:07 +08:00
Phoebe Wang
2e0588d5e1
Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.
2024-08-02 13:04:10 +08:00
Phoebe Wang
10bad2c8d7
[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-02 12:10:50 +08:00
Shengchen Kan
fd6faee5b3
[Driver,CodeGen] Report error when enabling 64-bit-only features on non-64-bit arch (#101151)
In front-end, now we detect for `-mapx-features=/-mapxf` and `-muintr`,
which is aligned with GCC

https://gcc.gnu.org/bugzilla/attachment.cgi?id=58698&action=diff

In backend, we just disable these 64-bit-only features silently, so that
there is no error for
`-march=native -m32` on APX-supported arch.

llvm-issue: https://github.com/llvm/llvm-project/issues/94810
GCC thread: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115978
2024-07-31 10:38:33 +08:00
Shengchen Kan
88e9bd822f [X86][Driver] Enable feature zu for -mapxf
This is follow-up for #78901 after validation.
Drop the comments for stability since zu is the last feature for cpuid APX_F.
2024-07-19 12:34:41 +08:00
James Y Knight
f0eb5587ce
Remove support for 3DNow!, both intrinsics and builtins. (#96246)
This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family
(2011). They were never much used, as they were effectively superseded
by the more-widely-implemented SSE (first implemented on the AMD side
in Athlon XP in 2001).

This is being done as a predecessor towards general removal of MMX
register usage. Since there is almost no usage of the 3DNow!
intrinsics, and no modern hardware even implements them, simple
removal seems like the best option.

(Clang half originally uploaded in https://reviews.llvm.org/D94213)

Works towards issue #41665 and issue #98272.
2024-07-16 12:08:48 -04:00
Shengchen Kan
8ad32ce738 [X86] Add sub-feature zu (zero upper) for APX
This is a follow-up patch for #74199
2024-06-25 09:25:32 +08:00
Shengchen Kan
45a7af7c99 [X86][Driver] Enable feature cf for -mapxf
This is follow-up for #78901 after validation.
2024-06-24 15:11:07 +08:00
Shengchen Kan
0f7b4b04a5 [X86][Driver] Enable feature ccmp,nf for -mapxf
This is follow-up for #78901 after validation.
2024-05-29 17:34:26 +08:00
Freddy Ye
4def1ce101
Reland "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93136)
This reverts commit aa4069ea96e5eb62bc8c7895b9d920f129611b3a.
2024-05-24 13:46:34 +08:00
Freddy Ye
aa4069ea96
Revert "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93123)
This reverts commit 282d2ab58f56c89510f810a43d4569824a90c538.
2024-05-23 10:25:23 +08:00
Freddy Ye
282d2ab58f
[X86] Remove knl/knm specific ISAs supports (#92883)
Cont. patch after https://github.com/llvm/llvm-project/pull/75580
2024-05-23 09:46:44 +08:00
Shengchen Kan
575177f610 [X86] Add sub-feature nf (no flags update) for APX
This is a follow-up patch for #74199
2024-05-11 15:55:59 +08:00
Shengchen Kan
85337df9e3
[X86][Driver] Enable feature ndd for -mapxf (#78901) 2024-01-22 12:30:25 +08:00
Shengchen Kan
6d6baef5c9
[X86] Support CFE flags for APX features (#74199)
Positive options: -mapx-features=<comma-separated-features>
Negative options: -mno-apx-features=<comma-separated-features>

-m[no-]apx-features is designed to be able to control separate APX
features.

Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>

Behaviour when positive and negative options are used together:

For boolean flags, the last one wins

-mapxf   -mno-apxf   -> -mno-apxf
-mno-apxf   -mapxf   -> -mapxf

For flags that take a set as arguments, it sets the mask by order of the
flags

-mapx-features=egpr,ndd  -mno-apx-features=egpr  ->   -egpr,+ndd
-mapx-features=egpr  -mno-apx-features=egpr,ndd  ->   -egpr,-ndd
-mno-apx-features=egpr  -mapx-features=egpr,ndd  ->   +egpr,+ndd
-mno-apx-features=egpr,ndd  -mapx-features=egpr  ->   -ndd,+egpr

The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
2023-12-04 19:22:56 +08:00
Phoebe Wang
f229ba4e8d
[X86][AVX10] Permit AVX512 options/features used together with AVX10 (#71318)
This patch relaxes the driver logic to permit combinations between
AVX512 and AVX10 options and makes sure we have a unified behavior
between options and features combination.

Here are rules we are following when handle these combinations:
1. evex512 can only be used for avx512xxx options/features. It will be
ignored if used without them;
2. avx512xxx and avx10.xxx are options in two worlds. Avoid to use them
together in any case. It will enable a common super set when they are
used together. E.g., "-mavx512f -mavx10.1-256" euqals "-mavx10.1-512".

Compiler emits warnings when user using combinations like "-mavx512f
-mavx10.1-256" in case they won't get unexpected result silently.

Function target feature attribute follows the same rule now. We have to
add "no-evex512" feature for intrinsics shared between AVX512 and AVX10.
We also add "no-evex512" for early ISAs like AVX etc., because some of
them are called by AVX512 intrinsics.
2023-11-10 15:21:05 +08:00
Phoebe Wang
cfbf0a500f
[X86][RFC] Support AVX10 options (#67278)
AVX10 Architecture Specification:
https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC:
https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
2023-10-19 07:52:50 +08:00
Freddy Ye
819ac45d1c
[X86] Add USER_MSR instructions. (#68944)
For more details about this instruction, please refer to the latest ISE
document:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
2023-10-16 10:12:53 +08:00
Phoebe Wang
24194090e1 [X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features
This is an alternative of D157485 and a pre-feature to support AVX10.

AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661

Based on the feedbacks from LLVM and GCC community, we have agreed to
start from supporting `-m[no-]evex512` on existing AVX512 features.
The option `-mno-evex512` can be used with `-mavx512xxx` to build
binaries that can run on both legacy AVX512 targets and AVX10-256.

There're still arguments about what's the expected behavior when this
option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We
decided to defer the support of `-mavx10.1` after we made consensus.
Or furthermore, we start from supporting AVX10.2 and not providing any
AVX10.1 options.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D159250
2023-09-08 22:47:22 +08:00
Phoebe Wang
0856efbf88 Revert "[X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features"
This reverts commit 7dd48cc24de2d54d40527432cbee8a9d97a8a4f7.

Causing buildbot failure.
2023-09-07 21:59:01 +08:00
Phoebe Wang
7dd48cc24d [X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features
This is an alternative of D157485 and a pre-feature to support AVX10.

AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661

Based on the feedbacks from LLVM and GCC community, we have agreed to
start from supporting `-m[no-]evex512` on existing AVX512 features.
The option `-mno-evex512` can be used with `-mavx512xxx` to build
binaries that can run on both legacy AVX512 targets and AVX10-256.

There're still arguments about what's the expected behavior when this
option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We
decided to defer the support of `-mavx10.1` after we made consensus.
Or furthermore, we start from supporting AVX10.2 and not providing any
AVX10.1 options.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D159250
2023-09-07 21:38:35 +08:00
Fangrui Song
5fd5f8027f [Driver] Mark m_x86_Features_Group options as TargetSpecific
so that they lead to an error when compiled for non-x86 targets.
Follow-up to D151590.

```
% aarch64-linux-gnu-gcc -c -mavx a.c
aarch64-linux-gnu-gcc: error: unrecognized command-line option ‘-mavx’
% clang --target=aarch64-unknown-linux-gnu -c -mavx a.c  # without this patch
clang: warning: argument unused during compilation: '-mavx' [-Wunused-command-line-argument]
...

% clang --target=aarch64-unknown-linux-gnu -c -mavx a.c  # with this patch
clang: error: unsupported option '-mavx' for target 'aarch64-unknown-linux-gnu'
```

As a workaround for https://github.com/llvm/llvm-project/issues/63270, we don't
report an error for -msse4.2.

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D156962
2023-08-03 19:04:53 -07:00
Fangrui Song
f39c399d9d [Driver] -###: exit with code 1 if hasErrorOccurred
The exit code for -### is inconsistent. Unrecognized options lead to
exit code 1, as expected. However, most others errors (including invalid
option value) lead to exit code 0, differing from GCC and most utilities.

This is a longstanding quirk of -###, and we didn't fix it because many
driver tests need adjustment.

Change -### to be similar to -fdriver-only -v and exit with code 1.

This requires fixing many driver tests, but the end result gives us
stronger tests.

* Existing `RUN: %clang -### ...` tests usually don't use `CHECK-NOT: error:` or `--implicit-check-not=error:`.
  If a change introduces an error, such a change usually cannot be detected.
* Many folks contributing new tests don't know `-fdriver-only -v`.
  To test no driver error/warning for new tests, they can use the familiar `-### -Werror`
  instead of `-fdriver-only -v -Werror`.

An incomplete list of prerequisite test improvement:

* 2f79bb10461d114783a1548201928549ace09755: add -nogpulib to some AMDGPU tests
* 9155e517e6e1cda474d0d0fa82f71696c325bc10: add --cuda-path= (test w/ and w/o /usr/local/cuda)
* 80765ede5bbcca1364c2d4ae06127011eaba6389: -mcpu=native may return either 0 or 1, depending on whether `--target=` specifies a native target
* abae53f43f0d1da8d8e421f4a628d7ec64d6e365: fix -fuse-ld=lld misuses (test w/o and w/o /usr/local/bin/ld.lld)
* ab68df505e5bb8808ee44f53044b50ca7575098e: add -resource-dir= and -fvisibility=hidden
 to some -fsanitize=cfi tests
* d5ca1602f64114f612ad5630f04e4aa90591c78d: --rtlib=platform without --unwindlib= may fail if CLANG_DEFAULT_UNWINDLIB=unwindlib

Reviewed By: jhuber6, yaxunl, dblaikie

Differential Revision: https://reviews.llvm.org/D156363
2023-08-01 13:23:51 -07:00
Fangrui Song
662c9ef180 Revert D156363 "[Driver] -###: exit with code 1 if hasErrorOccurred"
This reverts commit 8c3550b1a78fde7bf28f420da8447d9fde37017f.

clang/test/Driver/fsanitize.c has a mysterious failure worth
investigation.
2023-07-30 19:52:26 -07:00
Fangrui Song
8c3550b1a7 [Driver] -###: exit with code 1 if hasErrorOccurred
The exit code for -### is inconsistent. Unrecognized options lead to
exit code 1, as expected. However, most others errors (including invalid
option value) lead to exit code 0, differing from GCC and most utilities.

This is a longstanding quirk of -###, and we didn't fix it because many
driver tests need adjustment.

Change -### to be similar to -fdriver-only -v and exit with code 1.

This requires fixing many driver tests, but the end result gives us
stronger tests.

* Existing `RUN: %clang -### ...` tests usually don't use `CHECK-NOT: error:` or `--implicit-check-not=error:`.
  If a change introduces an error, such a change usually cannot be detected.
* Many folks contributing new tests don't know `-fdriver-only -v`.
  To test no driver error/warning for new tests, they can use the familiar `-### -Werror`
  instead of `-fdriver-only -v -Werror`.

An incomplete list of prerequisite test improvement:

* 2f79bb10461d114783a1548201928549ace09755: add -nogpulib to some AMDGPU tests
* 9155e517e6e1cda474d0d0fa82f71696c325bc10: add --cuda-path= (test w/ and w/o /usr/local/cuda)
* 80765ede5bbcca1364c2d4ae06127011eaba6389: -mcpu=native may return either 0 or 1, depending on whether `--target=` specifies a native target
* abae53f43f0d1da8d8e421f4a628d7ec64d6e365: fix -fuse-ld=lld misuses (test w/o and w/o /usr/local/bin/ld.lld)

Reviewed By: jhuber6, yaxunl, dblaikie

Differential Revision: https://reviews.llvm.org/D156363
2023-07-29 20:04:00 -07:00
Fangrui Song
2f372aecb5 Revert D156363 "[Driver] -###: exit with code 1 if hasErrorOccurred"
This reverts commit e39bf32b3bc2f0cc21d783ba789bd82553493875.

Some tests have different behaviors depent on whether certain directories/files are present on the host.
An incomplete list from https://lab.llvm.org/buildbot/#/builders/109/builds/70149

csky-toolchain.c
riscv*-toolchain.c
fuchsia.*
hip-*
ohos.c
2023-07-28 21:43:42 -07:00
Fangrui Song
e39bf32b3b [Driver] -###: exit with code 1 if hasErrorOccurred
The exit code for -### is inconsistent. Unrecognized options lead to
exit code 1, as expected. However, most others errors (including invalid
option value) lead to exit code 0, differing from GCC and most utilities.

This is a longstanding quirk of -###, and we didn't fix it because many
driver tests need adjustment.

Change -### to be similar to -fdriver-only -v and exit with code 1.

This requires fixing many driver tests, but the end result gives us
stronger tests.

* Existing `RUN: %clang -### ...` tests usually don't use `CHECK-NOT: error:` or `--implicit-check-not=error:`.
  If a change introduces an error, such a change usually cannot be detected.
* Many folks contributing new tests don't know `-fdriver-only -v`.
  To test no driver error/warning for new tests, they can use the familiar `-### -Werror`
  instead of `-fdriver-only -v -Werror`.

Reviewed By: jhuber6, yaxunl, dblaikie

Differential Revision: https://reviews.llvm.org/D156363
2023-07-28 20:31:39 -07:00
Freddy Ye
1c154bd755 [X86] Add AVX-VNNI-INT16 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155145
2023-07-20 14:31:16 +08:00
Freddy Ye
049d6a3f42 [X86] Add SM4 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D155148
2023-07-20 13:35:15 +08:00
Freddy Ye
c6f66de21a [X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D155147
2023-07-20 10:24:16 +08:00
Freddy Ye
fc3b7874b6 [X86] Add SHA512 instructions.
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D155146
2023-07-20 09:44:44 +08:00
Hans Wennborg
5160f6fefb Revert "[Driver] Mark m_x86_Features_Group options as TargetSpecific"
This broke cross-builds of llvm from x86_64 to arm64 mac, see
comment on
1d6c3e29f6

> so that they get an error on non-x86 targets.
> Follow-up to D151590.
>
> As a workaround for https://github.com/llvm/llvm-project/issues/63270, we don't
> report an error for -msse4.2.

This reverts commit 1d6c3e29f6aa45914faa7be00a939b8f550f38e9.
2023-06-13 12:50:51 +02:00
Fangrui Song
1d6c3e29f6 [Driver] Mark m_x86_Features_Group options as TargetSpecific
so that they get an error on non-x86 targets.
Follow-up to D151590.

As a workaround for https://github.com/llvm/llvm-project/issues/63270, we don't
report an error for -msse4.2.
2023-06-12 12:47:33 -07:00
Fangrui Song
c8c28ac5ca [Driver] Place -mharden-sls= in m_Group
Fix https://github.com/llvm/llvm-project/issues/63237

With only a link action, we claim all CompileOnly_Group options (including -f*,
-m*, -i*, etc). -mharden-sls= is not in a Group and therefore not claimed,
leading to a spurious -Wunused-command-line-argument warning, and after
5548843d692a92a7840f14002debc3cebcb3cdc3, an error.
2023-06-11 08:59:42 -07:00
Xiang1 Zhang
038b7e6b76 [X86] Support AMX Complex instructions
Reviewed By: Wang Pengfei

Differential Revision: https://reviews.llvm.org/D147420
2023-04-04 09:54:46 +08:00
Freddy Ye
aee2a35ac4 [X86] Add AVX-NE-CONVERT instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D135930
2022-10-31 23:39:38 +08:00
Freddy Ye
23f02693ec [X86] Add AVX-VNNI-INT8 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135938
2022-10-28 10:39:54 +08:00
Freddy Ye
0e720e6ada [X86] Add AVX-IFMA instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135932
2022-10-28 09:42:30 +08:00
Phoebe Wang
b51b90d6e2 [X86][1/2] SUPPORT RAO-INT
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Initial authored by Liu Chen (@LiuChen3)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D135951
2022-10-27 17:20:07 +08:00