23663 Commits

Author SHA1 Message Date
Simon Pilgrim
386b23f1fa [X86] Tag BMI/BMI2/TBM instructions scheduler classes
Put these under UNARY/BINOP ALU itinerary classes for now - seems to be a good average value

llvm-svn: 320064
2017-12-07 17:37:39 +00:00
Krzysztof Parzyszek
039d4d9286 [Hexagon] Generate HVX code for basic arithmetic operations
Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.

llvm-svn: 320063
2017-12-07 17:37:28 +00:00
Simon Pilgrim
d2e93e76b8 [X86][TBM] Add TBM scheduling tests
llvm-svn: 320062
2017-12-07 17:23:00 +00:00
Craig Topper
5db260fca4 [X86] Rename function in recently added test case to not be 'main' returning 'void'. NFC
llvm-svn: 320059
2017-12-07 17:02:49 +00:00
Simon Pilgrim
2983b46973 [X86] Tag SALC instructions scheduler class
Treat these the same as LAHF/SAHF (although its not a x86_64 instruction)

llvm-svn: 320055
2017-12-07 16:07:06 +00:00
Simon Pilgrim
ffce0d8fbc [X86] Add LAHF/SAHF scheduling test
llvm-svn: 320054
2017-12-07 16:04:20 +00:00
Simon Pilgrim
a383f84233 [X86] Add SALC scheduling test
llvm-svn: 320052
2017-12-07 15:46:58 +00:00
Simon Pilgrim
f1d599adb2 [X86] Tag LZCNT/TZCNT instructions scheduler classes
Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well

llvm-svn: 320051
2017-12-07 15:24:14 +00:00
Sanjay Patel
9012391af1 [DAGCombiner] eliminate shuffle of insert element
I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either 
repeating a scalar insertion at the same position in a vector or translated to a different 
element index.

Like the earlier patch, this could be an instcombine too, but since we opted to make this 
a DAG transform earlier, I've made this one a DAG patch too.

We do not need any legality checking because the new insert is identical to the existing 
insert except that it may have a different constant insertion operand.

The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the 
motivation for D38756.

Differential Revision: https://reviews.llvm.org/D40209

llvm-svn: 320050
2017-12-07 15:17:58 +00:00
Simon Pilgrim
ff5212091a [X86][FMA] Regenerate fma schedule tests
llvm-svn: 320048
2017-12-07 14:51:47 +00:00
Simon Pilgrim
60411d9a8c [X86] Tag RDRAND/RDSEED instruction scheduler classes
llvm-svn: 320045
2017-12-07 14:18:48 +00:00
Simon Pilgrim
9a2898ed22 [X86] Regenerate RDTSC codegen tests
llvm-svn: 320042
2017-12-07 13:50:29 +00:00
Dan Gohman
cdaa87dd2e [WebAssemby] Support main functions with alternate signatures.
WebAssembly requires caller and callee signatures to match, so the usual
C runtime trick of calling main and having it just work regardless of
whether main is defined as '()' or '(int argc, char *argv[])' doesn't
work. Extend the FixFunctionBitcasts pass to rewrite main to use the
latter form.

llvm-svn: 320041
2017-12-07 13:49:27 +00:00
Simon Pilgrim
439679c085 [X86][RDSEED] Add rdseed scheduling tests
llvm-svn: 320040
2017-12-07 13:47:17 +00:00
Simon Pilgrim
eb87fe62ec [X86][RDRAND] Add rdrand scheduling tests
llvm-svn: 320039
2017-12-07 13:46:47 +00:00
Nikolai Bozhenov
1cf9c54e5c [Nios2] final infrastructure to provide compilation of a return from a function
This patch includes all missing functionality needed to provide first
compilation of a simple program that just returns from a function.
I've added a test case that checks for "ret" instruction printed in assembly
output.

Patch by Andrei Grischenko (andrei.l.grischenko@intel.com)
Differential revision: https://reviews.llvm.org/D39688

llvm-svn: 320035
2017-12-07 12:35:02 +00:00
Andrew V. Tischenko
44cfc51415 Add proper BTVER2 sched support for MOV instr.
Differential Revision: https://reviews.llvm.org/D40345

llvm-svn: 320034
2017-12-07 11:19:49 +00:00
Francis Visoiu Mistrih
a8a83d150f [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
Work towards the unification of MIR and debug output by refactoring the
interfaces.

For MachineOperand::print, keep a simple version that can be easily called
from `dump()`, and a more complex one which will be called from both the
MIRPrinter and MachineInstr::print.

Add extra checks inside MachineOperand for detached operands (operands
with getParent() == nullptr).

https://reviews.llvm.org/D40836

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g'

llvm-svn: 320022
2017-12-07 10:40:31 +00:00
Mikael Holmen
b5deac444d Skip DBG instr in OptimizePHIs when looking for dead PHI cycles
Summary:
Changed use_instructions() to use_nodbg_instructions() when
building an instruction set.

We don't want the presence of debug info to affect the code
we generate.

Reviewers: dblaikie, Eugene.Zelenko, chandlerc, aprantl

Reviewed By: aprantl

Subscribers: aprantl, llvm-commits

Differential Revision: https://reviews.llvm.org/D40882

llvm-svn: 320010
2017-12-07 07:01:21 +00:00
Dan Gohman
5cf6473903 [WebAssembly] Don't try to emit size information for unsized types
Patch by John Sully!

Fixes PR35164.

Differential Revision: https://reviews.llvm.org/D39519

llvm-svn: 319991
2017-12-07 00:14:30 +00:00
Florian Hahn
5d6a4e43ba [AArch64] Add patterns to replace fsub fmul with fma fneg.
Summary:
This patch adds MachineCombiner patterns for transforming
(fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower
latency on micro architectures where fneg is cheap.

Patch based on work by George Steed.

Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma

Reviewed By: evandro

Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40306

llvm-svn: 319980
2017-12-06 22:48:36 +00:00
Krzysztof Parzyszek
d2967868be [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically
llvm-svn: 319978
2017-12-06 22:41:49 +00:00
Krzysztof Parzyszek
64533cf630 [Hexagon] Handle perfect shuffles on single vectors
llvm-svn: 319965
2017-12-06 21:25:03 +00:00
Dan Gohman
ad19047d83 [WebAssembly] Remove WASM_STACK_POINTER.
WASM_STACK_POINTER and the .stack_pointer directive are no longer needed
now that the stack pointer global is an import.

llvm-svn: 319956
2017-12-06 20:56:40 +00:00
Simon Pilgrim
9afbe77a91 [X86][AVX512] Tag mask reg op instruction scheduler classes
llvm-svn: 319945
2017-12-06 19:36:00 +00:00
Simon Pilgrim
7724b03cde [X86][SSE] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
llvm-svn: 319921
2017-12-06 18:47:37 +00:00
Simon Pilgrim
809c024b3d [X86][AVX2] Tag MASKMOV instruction scheduler classes
llvm-svn: 319915
2017-12-06 18:24:48 +00:00
Craig Topper
fa172a5251 [X86] Regenerate test for r319778
llvm-svn: 319914
2017-12-06 18:04:39 +00:00
Simon Pilgrim
df05251921 [X86][AVX512] Tag aligned/unaligned move instruction scheduler classes
llvm-svn: 319913
2017-12-06 17:59:26 +00:00
Simon Pilgrim
3ee91ade9b [X86][AVX] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
llvm-svn: 319912
2017-12-06 17:57:18 +00:00
Artem Belevich
a659d2590e [NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
Differential Revision: https://reviews.llvm.org/D40872

llvm-svn: 319909
2017-12-06 17:50:05 +00:00
Zvi Rackover
ffaed72089 AMDGPU Tests: Change a case to be run with -O0
D40231 requires to run case with -O0 to prevent InstructionSimplify from
transforming an extractelement with undef index.

llvm-svn: 319907
2017-12-06 17:40:09 +00:00
Krzysztof Parzyszek
7d37dd8902 [Hexagon] Generate HVX code for vector construction and access
Support for:
  - build vector,
  - extract vector element, subvector,
  - insert vector element, subvector,
  - shuffle.

llvm-svn: 319901
2017-12-06 16:40:37 +00:00
Simon Pilgrim
aa902be158 [X86][AVX512] Tag BROADCAST instruction scheduler classes
llvm-svn: 319900
2017-12-06 15:48:40 +00:00
Nirav Dave
7d8f3e0c93 [ARM][AArch64][DAG] Reenable post-legalize store merge
Reenable post-legalize stores with constant merging computation and
corresponding test case.

 * Properly truncate store merge constants
 * Disable merging of truncated stores floating points
 * Ensure merges of constant stores into a single vector are
   constructed from legal elements.

Reviewers: eastig, efriedma

Reviewed By: eastig

Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40701

llvm-svn: 319899
2017-12-06 15:30:13 +00:00
Simon Pilgrim
a9282309e5 [X86][AVX512] Regenerate vpmovm2*/vpmov*2m avx512 schedule tests
llvm-svn: 319895
2017-12-06 14:07:38 +00:00
Jonas Paulsson
19380bae05 [SystemZ] Bugfix in expandRxSBG()
Csmith discovered a program that caused wrong code generation with -O0:

When handling a SIGN_EXTEND in expandRxSBG(), RxSBG.BitSize may be less than
the Input width (if a truncate was previously traversed), so maskMatters()
should be called with a masked based on the width of the sign extend result
instead.

Review: Ulrich Weigand
llvm-svn: 319892
2017-12-06 13:53:24 +00:00
Vlad Tsyrklevich
0b40f21134 Revert "[DAGCombine] Move AND nodes to multiple load leaves"
This reverts commit r319773. It was causing some buildbots to hang, e.g.
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-android/builds/5589

llvm-svn: 319867
2017-12-06 01:16:08 +00:00
Simon Pilgrim
d495301414 [X86][AVX512] Tag BLENDM instruction scheduler classes
llvm-svn: 319833
2017-12-05 21:05:25 +00:00
Simon Pilgrim
b69dae42e3 [X86][AVX512] Tag GATHER/SCATTER instruction scheduler classes
NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed.
llvm-svn: 319829
2017-12-05 20:47:11 +00:00
Matt Arsenault
8ae38bc0bd AMDGPU: Fix SDWA crash on inline asm
This was only searching for explicit defs,
and asserting for any implicit or variadic
instruction defs, like inline asm.

llvm-svn: 319826
2017-12-05 20:32:01 +00:00
Hans Wennborg
5df9f0878b Re-commit r319490 "XOR the frame pointer with the stack cookie when protecting the stack"
The patch originally broke Chromium (crbug.com/791714) due to its failing to
specify that the new pseudo instructions clobber EFLAGS. This commit fixes
that.

> Summary: This strengthens the guard and matches MSVC.
>
> Reviewers: hans, etienneb
>
> Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D40622

llvm-svn: 319824
2017-12-05 20:22:20 +00:00
Ulrich Weigand
5bfed6cb7c [SystemZ] Validate shifted compare value in adjustForTestUnderMask
When folding a shift into a test-under-mask comparison, make sure that
there is no loss of precision when creating the shifted comparison
value.  This usually never happens, except for certain always-true
comparisons in unoptimized code.

Fixes PR35529.

llvm-svn: 319818
2017-12-05 19:42:07 +00:00
Simon Pilgrim
833c260a4b [X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classes
llvm-svn: 319815
2017-12-05 19:21:28 +00:00
Matt Arsenault
7f0a527300 AMDGPU: Fix infinite loop with dbg_value
Surprisingly SIOptimizeExecMaskingPreRA can infinite loop
in some case with DBG_VALUE. Most tests using dbg_value are
run at -O0, so don't run this pass. This seems to only
happen when the value argument is undef.

llvm-svn: 319808
2017-12-05 18:23:17 +00:00
Simon Pilgrim
65f805fe30 [X86][X87] Tag FCMOV instruction scheduler classes
llvm-svn: 319804
2017-12-05 18:01:26 +00:00
Dan Gohman
c2c997718d [WebAssembly] Implement WASM_STACK_POINTER.
Use the .stack_pointer directive to implement WASM_STACK_POINTER for
specifying a global variable to be the stack pointer.

llvm-svn: 319797
2017-12-05 17:23:43 +00:00
Dan Gohman
f7172f4ab0 [WebAssembly] Don't emit .import_global for the wasm target.
.import_global is used by the ELF-based target and not needed by the wasm
target.

llvm-svn: 319796
2017-12-05 17:21:57 +00:00
Jina Nahias
51c1a627c2 [x86][AVX512] Lowering kunpack intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D39719), implements the lowering of X86 kunpack intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D39720

Change-Id: I4088d9428478f9457f6afddc90bd3d66b3daf0a1
llvm-svn: 319778
2017-12-05 15:42:56 +00:00
Bjorn Pettersson
5abbad7999 Add REQUIRES asserts in combine_loads_from_build_pair.ll
A fixup of r319771, that was causing buildbot failures.

llvm-svn: 319775
2017-12-05 15:26:01 +00:00