549399 Commits

Author SHA1 Message Date
Yi Kong
1ff7c8bf0d [compiler-rt] Fix musl build
The change in PR #154268 introduced a dependency on the `__GLIBC_PREREQ`
macro, which is not defined in musl libc. This caused the build to fail
in environments using musl.

This patch fixes the build by including
`sanitizer_common/sanitizer_glibc_version.h`. This header provides a
fallback definition for `__GLIBC_PREREQ` when LLVM is built against
non-glibc C libraries, resolving the compilation error.
2025-08-21 15:19:06 +09:00
Sergei Barannikov
b96d5c2452
[TableGen][DecoderEmitter] Outline InstructionEncoding constructor (NFC) (#154673)
It is going to grow, so it makes sense to move its definition
out of class. Instead, inline `populateInstruction()` into it.
Also, rename a couple of methods to better convey their meaning.
2025-08-21 06:08:57 +00:00
Abhishek Kaushik
62aaa96d6f
[SDAG[[X86] Added method to scalarize STRICT_FSETCC (#154486)
Fixes #154485
2025-08-21 11:27:27 +05:30
Carlos Galvez
3baddbbb0a
Do not trigger -Wmissing-noreturn on lambdas prior to C++23 (#154545)
Fixes #154493

Co-authored-by: Carlos Gálvez <carlos.galvez@zenseact.com>
2025-08-21 07:30:57 +02:00
Jim Lin
3a715107c2 [RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
All of them use the same argstr "$vd, $vs1, $vs2".
2025-08-21 13:12:46 +08:00
Craig Topper
2d3d8df0e0 [RISCV] Use RVPTernary_rrr for a few more instructions.
This doesn't really affect the assembler, but will
be important when we eventually do codegen.
2025-08-20 21:13:40 -07:00
Sergei Barannikov
d6679d5a5f
[Target] Remove SoftFail field on targets that don't use it (NFC) (#154659)
That is, on all targets except ARM and AArch64.
This field used to be required due to a bug, it was fixed long ago
by 23423c0ea8d414e56081cb6a13bd8b2cc91513a9.
2025-08-21 05:21:42 +03:00
Jordan Rupprecht
918c0ac762
[bazel] Port #154616: LDBG in ConvertToLLVMPass (#154661) 2025-08-20 21:21:14 -05:00
Jordan Rupprecht
90d601d50b
[bazel][LLVMIR] Port #145899: Add target attrs (#154660) 2025-08-21 01:59:41 +00:00
Sirui Mu
91569fa030
[CIR][NFC] Use Op::create to create CIR operations in CIRGenBuilder (#154540) 2025-08-21 09:46:45 +08:00
Aiden Grossman
c811f522f6
[ProfCheck] Add list of xfail tests (#154655)
This patch contains a list of tests that are currently failing in the
LLVM_ENABLE_PROFCHECK=ON build. This enables passing them to lit through
the LIT_XFAIL env variable. This is necessary for getting a buildbot
spun up to catch regressions while work is being done to fix the
existing issues.

We need to keep this in the LLVM tree so that tests can be removed from
the list at the same time the passes causing issues are fixed.

Issue #147390
2025-08-21 01:28:05 +00:00
Matt Arsenault
e414585545
AMDGPU: Add baseline test for mfma rewrite with phi (#153021) 2025-08-21 10:25:05 +09:00
Matt Arsenault
bcf41e03c7
AMDGPU: Add baseline test for vgpr mfma with copied-from AGPR (#153020) 2025-08-21 10:24:27 +09:00
Matt Arsenault
eefad7438c
AMDGPU: Handle rewriting VGPR MFMA to AGPR with subregister copies (#153019)
This should address the case where the result isn't fully used,
resulting in partial copy bundles from the MFMA result.
2025-08-21 01:17:03 +00:00
Jim Lin
fd28257195
[DAGCombiner] Fold umax/umin operations with vscale operands (#154461)
If umax/umin operations with vscale operands, that can be constant
folded.
2025-08-21 09:15:40 +08:00
PiJoules
3c8652e737
[compiler-rt][Fuchsia] Change GetMaxUserVirtualAddress to invoke syscall (#153309)
LSan was recently refactored to call GetMaxUserVirtualAddress for
diagnostic purposes. This leads to failures for some of our downstream
tests which only run with lsan. This occurs because
GetMaxUserVirtualAddress depends on setting up shadow via a call to
__sanitizer_shadow_bounds, but shadow bounds aren't set for standalone
lsan because it doesn't use shadow. This updates the function to invoke
the same syscall used by __sanitizer_shadow_bounds calls for getting the
memory limit. Ideally this function would only be called once since we
only need to get the bounds once.

More context in https://fxbug.dev/437346226.
2025-08-20 18:06:19 -07:00
Craig Topper
8cb6bfe05a [RISCV] Reduce ManualCodeGen for RVV intrinsics with rounding mode. NFC
Operate directly on the existing Ops vector instead of copying to
a new vector. This is similar to what the autogenerated codegen
does for other intrinsics.
2025-08-20 17:53:46 -07:00
Matt Arsenault
744cd8a9c6
AMDGPU: Add some baseline test for mfma rewrite with subregister copies (#153018)
Currently only cases rooted at a full copy of an MFMA result are
handled.
Prepare to relax that by testing more intricate subregister usage.

Currently only full copies are handled, add some tests to help work
towards handling subregisters.
2025-08-21 00:39:39 +00:00
Matt Arsenault
156f3fce54
AMDGPU: Handle rewriting VGPR MFMAs with immediate src2 (#153016) 2025-08-21 09:09:24 +09:00
Matt Arsenault
3a0fa12752
DAG: Handle half spanning extract_subvector in type legalization (#154101)
Previously it would just assert if the extract needed elements from
both halves. Extract the individual elements from both halves and
create a new vector, as the simplest implementation. This could
try to do better and create a partial extract or shuffle (or
maybe that's best left for the combiner to figure out later).

Fixes secondary issue noticed as part of #153808
2025-08-21 00:05:12 +00:00
Elvis Wang
d611a9ca15
[LV][VPlan] Reduce register usage of VPEVLBasedIVPHIRecipe. (#154482)
`VPEVLBasedIVPHIRecipe` will lower to VPInstruction scalar phi and
generate scalar phi. This recipe will only occupy a scalar register just
like other phi recipes.

This patch fix the register usage for `VPEVLBasedIVPHIRecipe` from
vector
to scalar which is close to generated vector IR.

https://godbolt.org/z/6Mzd6W6ha shows that no register spills when
choosing `<vscale x 16>`.

Note that this test is basically copied from AArch64.
2025-08-21 07:39:01 +08:00
Shih-Po Hung
cf0e86118d
[VPlan] Handle canonical VPWidenIntOrFpInduction in branch-condition simplification (#153539)
SimplifyBranchConditionForVFAndUF only recognized canonical IVs and a
few PHI
recipes in the loop header. With more IV-step optimizations,
the canonical widen-canonical-iv can be replaced by a canonical
VPWidenIntOrFpInduction,
which the pass did not handle, causing regressions (missed
simplifications).

This patch replaces canonical VPWidenIntOrFpInduction with a StepVector
in the vector preheader
since the vector loop region only executes once.
2025-08-21 07:34:54 +08:00
Kazu Hirata
9aae8ef329
[Scalar] Use SmallPtrSet directly instead of SmallSet (NFC) (#154473)
I'm trying to remove the redirection in SmallSet.h:

template <typename PointeeType, unsigned N>
class SmallSet<PointeeType*, N> : public SmallPtrSet<PointeeType*, N>
{};

to make it clear that we are using SmallPtrSet.  There are only
handful places that rely on this redirection.

This patch replaces SmallSet to SmallPtrSet where the element type is
a pointer.
2025-08-20 16:30:39 -07:00
Kazu Hirata
7be06dbd43
[lldb] Use SmallPtrSet directly instead of SmallSet (NFC) (#154472)
I'm trying to remove the redirection in SmallSet.h:

template <typename PointeeType, unsigned N>
class SmallSet<PointeeType*, N> : public SmallPtrSet<PointeeType*, N>
{};

to make it clear that we are using SmallPtrSet.  There are only
handful places that rely on this redirection.

This patch replaces SmallSet to SmallPtrSet where the element type is
a pointer.
2025-08-20 16:30:31 -07:00
Kazu Hirata
8a5b6b302e
[flang] Use SmallPtrSet directly instead of SmallSet (NFC) (#154471)
I'm trying to remove the redirection in SmallSet.h:

template <typename PointeeType, unsigned N>
class SmallSet<PointeeType*, N> : public SmallPtrSet<PointeeType*, N>
{};

to make it clear that we are using SmallPtrSet.  There are only
handful places that rely on this redirection.

This patch replaces SmallSet to SmallPtrSet where the element type is
a pointer.
2025-08-20 16:30:24 -07:00
Min-Yih Hsu
db0eceaa8b
[AMDGPU] Fix uncaught changes made by AMDGPUPreloadKernelArgumentsPass (#154645)
#153975 added a new test,
`test/CodeGen/AMDGPU/disable-preload-kernargs.ll`, that triggers an
assertion under `LLVM_ENABLE_EXPENSIVE_CHECKS` complaining about not
invalidating analyses even when the Pass made changes. It was caused by
the fact that the Pass only invalidates the analyses when number of
explicit arguments is greater than zero, while it is possible that some
functions will be removed even when there isn't any explicit argument,
hence the missed invalidation.
2025-08-20 16:23:23 -07:00
Matt Arsenault
ff5f396dac
AMDGPU: Handle rewriting non-tied MFMA to AGPR form (#153015)
If src2 and dst aren't the same register, to fold a copy
to AGPR into the instruction we also need to reassign src2
to an available AGPR. All the other uses of src2 also need
to be compatible with the AGPR replacement in order to avoid
inserting other copies somewhere else.

Perform this transform, after verifying all other uses are
compatible with AGPR, and have an available AGPR available at
all points (which effectively means rewriting a full chain of
mfmas and load/store at once).
2025-08-21 08:16:56 +09:00
Renaud Kauffmann
3856bb6bbf
[flang] [acc] Adding allocation to the recipe of scalar allocatables (#154643)
Currently the privatization recipe of a scalar allocatable is as follow:

```
 acc.private.recipe @privatization_ref_box_heap_i32 : !fir.ref<!fir.box<!fir.heap<i32>>> init {
  ^bb0(%arg0: !fir.ref<!fir.box<!fir.heap<i32>>>):
    %0 = fir.alloca !fir.box<!fir.heap<i32>>
    %1:2 = hlfir.declare %0 {uniq_name = "acc.private.init"} : (!fir.ref<!fir.box<!fir.heap<i32>>>) -> (!fir.ref<!fir.box<!fir.heap<i32>>>, !fir.ref<!fir.box<!fir.heap<i32>>>)
    acc.yield %1#0 : !fir.ref<!fir.box<!fir.heap<i32>>>
  }
```

This change adds the allocation for the scalar.
2025-08-20 16:04:57 -07:00
Mehdi Amini
62b29d9f76
[MLIR] Adopt LDBG() debug macro in BytecodeWriter.cpp (NFC) (#154642) 2025-08-20 22:45:39 +00:00
Mehdi Amini
908eebcb93
[MLIR] Adopt LDBG() macro in PDL ByteCodeExecutor (NFC) (#154641) 2025-08-20 22:40:52 +00:00
Ely Ronnen
8b64cd8be2
[lldb-dap] Add module symbol table viewer to VS Code extension #140626 (#153836)
- VS Code extension:
- Add module symbol table viewer using
[Tabulator](https://tabulator.info/) for sorting and formatting rows.
  - Add context menu action to the modules tree.
 - lldb-dap
   -  Add `DAPGetModuleSymbolsRequest` to get symbols from a module.
 
Fixes #140626

[Screencast From 2025-08-15
19-12-33.webm](https://github.com/user-attachments/assets/75e2f229-ac82-487c-812e-3ea33a575b70)
2025-08-21 00:31:48 +02:00
Joseph Huber
27fc9671f9 Revert "[libc] Enable wide-read memory operations by default on Linux (#154602)"
This reverts commit c80d1483c6d787edf62ff9e86b1e97af5eb5abf9.
2025-08-20 17:27:13 -05:00
Craig Topper
2cb7c46bf0 [RISCV] Add missing 'OrP' to comment in RISCVInstrInfoZb.td. NFC 2025-08-20 15:27:03 -07:00
Joseph Huber
c80d1483c6
[libc] Enable wide-read memory operations by default on Linux (#154602)
Summary:
This patch changes the linux build to use the wide reads on the memory
operations by default. These memory functions will now potentially read
outside of the bounds explicitly allowed by the current function. While
technically undefined behavior in the standard, plenty of C library
implementations do this. it will not cause a segmentation fault on linux
as long as you do not cross a page boundary, and because we are only
*reading* memory it should not have atomic effects.
2025-08-20 17:17:12 -05:00
Craig Topper
ac8f0bb070 [RISCV] Reduce ManualCodeGen for segment load/store intrinsics. NFC
Operate directly on the existing Ops vector instead of copying to
a new vector. This is similar to what the autogenerated codegen
does for other intrinsics.

This reduced the clang binary size by ~96kb on my local Release+Asserts
build.
2025-08-20 15:02:24 -07:00
Sergei Barannikov
46343ca374
[TableGen][DecoderEmitter] Add DecoderMethod to InstructionEncoding (NFC) (#154477)
We used to abuse Operands list to store instruction encoding's
DecoderMethod there. Let's store it in the InstructionEncoding class
instead, where it belongs.
2025-08-20 21:59:59 +00:00
Mehdi Amini
dbbd3f0d07
[MLIR] Adopt LDBG() macro in Affine/Analysis/Utils.cpp (NFC) (#154626) 2025-08-20 21:56:03 +00:00
Alan Zhao
904b4f5a27
[clang][timers][modules] Fix a timer being started when it's running (#154231)
`ASTReader::FinishedDeserializing()` calls
`adjustDeductedFunctionResultType(...)` [0], which in turn calls
`FunctionDecl::getMostRecentDecl()`[1]. In modules builds,
`getMostRecentDecl()` may reach out to the `ASTReader` and start
deserializing again. Starting deserialization starts `ReadTimer`;
however, `FinishedDeserializing()` doesn't call `stopTimer()` until
after it's call to `adjustDeductedFunctionResultType(...)` [2]. As a
result, we hit an assert checking that we don't start an already started
timer [3]. To fix this, we simply don't start the timer if it's already
running.

Unfortunately I don't have a test case for this yet as modules builds
are notoriously difficult to reduce.

[0]:
4d2288d318/clang/lib/Serialization/ASTReader.cpp (L11053)
[1]:
4d2288d318/clang/lib/AST/ASTContext.cpp (L3804)
[2]:
4d2288d318/clang/lib/Serialization/ASTReader.cpp (L11065-L11066)
[3]:
4d2288d318/llvm/lib/Support/Timer.cpp (L150)
2025-08-20 21:53:43 +00:00
Kazu Hirata
55551da200
[lldb] Add missing case statements for SubstBuiltinTemplatePack (#154606)
This patch fixes:

lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4148:11:
error: enumeration value 'SubstBuiltinTemplatePack' not handled in
switch [-Werror,-Wswitch]
4148 |   switch (qual_type->getTypeClass()) {
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~

lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4852:11:
error: enumeration value 'SubstBuiltinTemplatePack' not handled in
switch [-Werror,-Wswitch]
4852 |   switch (qual_type->getTypeClass()) {
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~

lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:5153:11:
error: enumeration value 'SubstBuiltinTemplatePack' not handled in
switch [-Werror,-Wswitch]
5153 |   switch (qual_type->getTypeClass()) {
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~
2025-08-20 14:53:28 -07:00
Gang Chen
575fad2892
[AMDGPU] Upstream the Support for array of named barriers (#154604) 2025-08-20 14:53:03 -07:00
Mehdi Amini
d20a74e631
[MLIR] Adopt LDBG() macro in BasicPtxBuilderInterface.cpp (NFC) (#154625) 2025-08-20 21:51:17 +00:00
Mehdi Amini
4be19e27b5
[MLIR] Adopt LDBG() debug macros in Affine LoopAnalysis.cpp (NFC) (#154621) 2025-08-20 21:45:42 +00:00
Steven Wu
deab049b5c
[CAS] Add ActionCache to LLVMCAS Library (#114097)
ActionCache is used to store a mapping from CASID to CASID. The current
implementation of the ActionCache can only be used to associate the
key/value from the same hash context.

ActionCache has two operations: `put` to store the key/value and `get`
to
lookup the key/value mapping. ActionCache uses the same TrieRawHashMap
data structure to store the mapping, where is CASID of the key is the
hash to index the map.

While CASIDs for key/value are often associcate with actual CAS
ObjectStore, it doesn't provide the guarantee of the existence of such
object in any ObjectStore.
2025-08-20 14:42:44 -07:00
Ramkumar Ramachandra
0db57ab586
[VPlan] Improve code using onlyScalarValuesUsed (NFC) (#154564) 2025-08-20 22:38:00 +01:00
Julian Lettner
484d0408f9
[lldb] Fix source line annotations for libsanitizers traces (#154247)
When providing allocation and deallocation traces,
the ASan compiler-rt runtime already provides call
addresses (`TracePCType::Calls`).

On Darwin, system sanitizers (libsanitizers)
provides return address.  It also discards a few
non-user frames at the top of the stack, because
these internal libmalloc/libsanitizers stack
frames do not provide any value when diagnosing
memory errors.

Introduce and add handling for
`TracePCType::ReturnsNoZerothFrame` to cover this
case and enable libsanitizers traces line-level
testing.

rdar://157596927

---
Commit 1 is a mechanical refactoring to introduce
and adopt `TracePCType` enum to replace
`pcs_are_call_addresses` bool.  It preserve the
current behavior:
```
pcs_are_call_addresses:
  false  ->  TracePCType::Returns (default)
  true   ->  TracePCType::Calls
``` 

Best reviewed commit by commit.
2025-08-20 14:33:27 -07:00
Florian Hahn
7d33743324
[LV] Add tests for narrowing interleave groups with scalable vectors. 2025-08-20 22:31:24 +01:00
Andy Kaylor
59b33242af
[CIR][NFC] Fix warning in MemOrder lowering (#154609)
This fixes a warning about having a default case in a fully covered enum
switch statement.
2025-08-20 14:30:22 -07:00
Mehdi Amini
6445a75c98
[MLIR] Update MLIRContext to use the LDBG() style debug macro (NFC) (#154619) 2025-08-20 21:30:11 +00:00
Mehdi Amini
ffbc8da8b5
[MLIR] Migrate LICM utils to the LDBG() macro style logging (NFC) (#154615) 2025-08-20 21:29:50 +00:00
Mehdi Amini
780750bbf9
[MLIR] Adopt LDBG() debug macro in ConvertToLLVMPass (NFC) (#154616) 2025-08-20 21:29:35 +00:00