507991 Commits

Author SHA1 Message Date
Ahmed Bougacha
2eb6e30fe8
[clang] Wire -fptrauth-returns to "ptrauth-returns" fn attribute. (#102416)
We already ended up with -fptrauth-returns, the feature macro, the lang
opt, and the actual backend lowering.

The only part left is threading it all through PointerAuthOptions, to
drive the addition of the "ptrauth-returns" attribute to generated
functions.
While there, do minor cleanup on ptrauth-function-attributes.c.

This also adds ptrauth_key_return_address to ptrauth.h.
2024-08-09 11:49:50 -07:00
Craig Topper
ca7ad38ca0
[RISCV] Remove riscv-experimental-rv64-legal-i32. (#102509)
This has received no development work in a while and is slowly bit
rotting as new extensions are added.

At the moment, I don't think this is viable without adding a new
invariant that 32 bit values are always in sign extended form like
Mips64 does. We are very dependent on computeKnownBits and
ComputeNumSignBits in SelectionDAG to remove sign extends created for
ABI reasons. If we can't propagate sign bit information through 64-bit
values in SelectionDAG, we can't effectively clean up those extends.
2024-08-09 11:48:48 -07:00
Craig Topper
31c75a124b
[RISCV] Move PseudoVSET(I)VLI expansion to use PseudoInstExpansion. (#102496)
Instead of expanding in RISCVExpandPseudoInsts, expand during
MachineInstr to MCInst lowering.

We weren't doing anything in expansion other than copying operands.
2024-08-09 11:47:06 -07:00
Alex MacLean
ccc31278bd
[NVPTX] support switch statement with brx.idx (reland) (#102550)
Add custom lowering for `BR_JT` DAG nodes to the `brx.idx` PTX
instruction ([PTX ISA 9.7.13.4. Control Flow Instructions: brx.idx]
(https://docs.nvidia.com/cuda/parallel-thread-execution/#control-flow-instructions-brx-idx)).
Depending on the heuristics in DAG selection, `switch` statements may
now be lowered using `brx.idx`.

Note: this fixes the previous issue in #102400 by adding the isBarrier
attribute to BRX_END
2024-08-09 11:46:37 -07:00
aaryanshukla
b6cbd014b9
[libc][newhdrgen]sorted function names in yaml (#102544) 2024-08-09 11:27:36 -07:00
Thorsten Schütt
6b77531123
[GlobalIsel] Combine G_ADD and G_SUB with constants (#97771) 2024-08-09 20:14:32 +02:00
Fangrui Song
edf45e4edd
Suppress spurious warnings due to R_RISCV_SET_ULEB128
llvm-objdump -S issues unnecessary warnings for RISC-V relocatable files
containing .debug_loclists or .debug_rnglists sections with ULEB128
relocations. This occurred because `DWARFObjInMemory` verifies support for all
relocation types, triggering warnings for unsupported ones.

```
% llvm-objdump -S a.o
...
0000000000000000 <foo>:
warning: failed to compute relocation: R_RISCV_SUB_ULEB128, Invalid data was encountered while parsing the file
warning: failed to compute relocation: R_RISCV_SET_ULEB128, Invalid data was encountered while parsing the file
...
```

This change fixes #101544 by declaring support for the two ULEB128
relocation types, silencing the spurious warnings.

---

In DWARF v5 builds, DW_LLE_offset_pair/DW_RLE_offset_pair might be
generated in .debug_loclists/.debug_rnglists with ULEB128 relocations.
They are only read by llvm-dwarfdump to dump section content and verbose
DW_AT_location/DW_AT_ranges output for relocatable files.

The DebugInfoDWARF user (e.g. DWARFDebugRnglists.cpp) calls
`Data.getULEB128` without checking the ULEB128 relocations, as the
unrelocated value holds meaning (refer to the assembler
implementation https://reviews.llvm.org/D157657). This differs from
`.quad .Lfoo`, which requires relocation reading (e.g.
https://reviews.llvm.org/D74404).

Pull Request: https://github.com/llvm/llvm-project/pull/101607
2024-08-09 10:59:20 -07:00
Joshua Baehring
9f3ff8d28a
[scudo] Separated committed and decommitted entries. (#101409)
Initially, the LRU list stored all mapped entries with no distinction
between the committed (non-madvise()'d) entries and decommitted
(madvise()'d) entries. Now these two types of entries re separated into
two lists, allowing future cache logic to branch depending on whether or
not entries are committed or decommitted. Furthermore, the retrieval
algorithm will prioritize committed entries over decommitted entries.
Specifically, committed entries that satisfy the MaxUnusedCachePages
requirement are retrieved before optimal-fit, decommitted entries.

This commit addresses the compiler errors raised
[here](https://github.com/llvm/llvm-project/pull/100818#issuecomment-2261043261).
2024-08-09 10:56:07 -07:00
yingopq
e711a0c80f
[MIPS] Fix missing ANDI optimization (#97689)
1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to (andi
(truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to (truncate
(dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fixes https://github.com/llvm/llvm-project/issues/42826
2024-08-09 18:55:21 +01:00
Joel E. Denny
1ea0865dd6
[Clang] Add env var for nvptx-arch/amdgpu-arch timeout (#102521)
When working on very busy systems, check-offload frequently fails many
tests with this diagnostic:

```
clang: error: cannot determine amdgcn architecture: /tmp/llvm/build/bin/amdgpu-arch: Child timed out: ; consider passing it via '-march'
```

This patch accepts the environment variable
`CLANG_TOOLCHAIN_PROGRAM_TIMEOUT` to set the timeout. It also increases
the timeout from 10 to 60 seconds.
2024-08-09 13:39:29 -04:00
Thurston Dang
7ede1c4973
[asan] Switch allocator to dynamic base address (#98511)
This ports a fix from memprof (https://github.com/llvm/llvm-project/pull/98510), which has a shadow mapping that is similar to ASan (8 bytes of shadow memory per 64 bytes of app memory). This patch changes the allocator to dynamically choose a base address, as suggested by Vitaly for memprof. This simplifies ASan's #ifdef's and avoids potential conflict in the event that ASan were to switch to a dynamic shadow offset in the future [1].

[1] Since shadow memory is mapped before the allocator is mapped:
- dynamic shadow and fixed allocator (old memprof): could fail if
"unlucky" (e.g., https://lab.llvm.org/buildbot/#/builders/66/builds/1361/steps/17/logs/stdio)
- dynamic shadow and dynamic allocator (HWASan; current memprof): always works
- fixed shadow and fixed allocator (current ASan): always works, if
constants are carefully chosen
- fixed shadow and dynamic allocator (ASan with this patch): always works
2024-08-09 10:36:50 -07:00
Shilei Tian
2fe61a5acf
[AMDGPU] Move AMDGPUAttributorPass to full LTO post link stage (#102086)
Currently `AMDGPUAttributorPass` is registered in default optimizer
pipeline.
This will allow the pass to run in default pipeline as well as at
thinLTO post
link stage. However, it will not run in full LTO post link stage. This
patch
moves it to full LTO.
2024-08-09 13:35:00 -04:00
aaryanshukla
8c81fb6167
[libc][math][c23] Add fadd{l,f128} C23 math functions (#102531)
Co-authored-by: OverMighty <its.overmighty@gmail.com>
2024-08-09 10:26:09 -07:00
Yijia Gu
95820ca263 [mlir][bazel] revert bazel rule change for DLTITransformOps 2024-08-09 10:18:18 -07:00
Thurston Dang
cb5ec3796a
[msan] Support vst{2,3,4}_lane instructions (#101215)
This generalizes MSan's Arm NEON vst support, to include the
lane-specific variants.

This also updates the test from
https://github.com/llvm/llvm-project/pull/100645.
2024-08-09 10:16:38 -07:00
Renato Golin
7752fec607 Revert "[MLIR][DLTI][Transform] Introduce transform.dlti.query (#101561)"
This reverts commit 8f21ff9bd89fb7c8bbfdc4426b65dcd9ababf3ce.

Crashed CI builds
2024-08-09 18:11:36 +01:00
Simon Pilgrim
37c66838bd [X86] pr57673.ll - generate MIR test checks 2024-08-09 18:07:37 +01:00
Andrzej Warzyński
5123f2c60a
[mlir][vector][test] Split tests from vector-transfer-flatten.mlir (#102584)
Move tests that exercise DropUnitDimFromElementwiseOps and
DropUnitDimsFromTransposeOp to a dedicated file.

While these patterns are collected under populateFlattenVectorTransferPatterns
(and are tested via -test-vector-transfer-flatten-patterns), they can actually
be tested without the xfer Ops, and hence the split.

Note, this is mostly just moving tests from one file to another. The only real
change is the removal of the following check-lines:

```mlir
//   CHECK-128B-NOT:   memref.collapse_shape
```

These were added specifically to check the "flattening" logic (which introduces
`memref.collapse_shape`). However, these tests were never meant to test that
logic (in fact, that's the reason I am moving them to a different file) and
hence are being removed as copy&paste errors.

I also removed the following TODO:

```mlir
/// TODO: Potential duplication with tests from:
///   * "vector-dropleadunitdim-transforms.mlir"
///   * "vector-transfer-drop-unit-dims-patterns.mlir"
```
I've checked what patterns are triggered in those test files and neither
DropUnitDimFromElementwiseOps nor DropUnitDimsFromTransposeOp does.
2024-08-09 18:04:25 +01:00
Yijia Gu
6f19a7b94a [mlir][bazel] add bazel rule for DLTITransformOps 2024-08-09 10:00:53 -07:00
Matt Arsenault
23209d1c1a OpenMPOpt: Remove dead include 2024-08-09 20:52:27 +04:00
Eli Friedman
2f8f58dd17
[IR] Add method to GlobalVariable to change type of initializer. (#102553)
With opaque pointers, nothing directly uses the value type, so we can
mutate it if we want. This avoid doing a complicated RAUW dance.
2024-08-09 09:22:40 -07:00
Valentin Clement (バレンタイン クレメン)
5c016bf40e
[flang][cuda] Force default allocator in device code (#102238) 2024-08-09 09:18:34 -07:00
Kazu Hirata
f4fb735840
[llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (#102578) 2024-08-09 09:15:42 -07:00
Rolf Morel
8f21ff9bd8
[MLIR][DLTI][Transform] Introduce transform.dlti.query (#101561)
This transform op makes it possible to query attributes associated to IR
by means of the DLTI dialect.

The op takes both a `key` and a target `op` to perform the query at.
Facility functions automatically find the closest ancestor op which
defines the appropriate DLTI interface or has an attribute implementing
a DLTI interface. By default the lookup uses the data layout interfaces
of DLTI. If the optional `device` parameter is provided, the lookup
happens with respect to the interfaces for TargetSystemSpec and
TargetDeviceSpec.

This op uses new free-standing functions in the `dlti` namespace to not
only look up specifications via the `DataLayoutSpecOpInterface` and on
`ModuleOp`s but also on any ancestor op that has an appropriate DLTI
attribute.
2024-08-09 17:09:25 +01:00
Ivan Kosarev
52220c295a
[AMDGPU][AsmParser][NFC] Remove a misleading comment. (#102604)
The work of ParseRegularReg() should remain to be parsing the register
as it was specified, and not to try translate it to anything else.

It's up to operand predicates to decide on what is and is not an
acceptable register for an operand, including considering its expected
register class, and for the rest of the AsmParser infrastructure to
handle it respectively from there on.
2024-08-09 16:52:19 +01:00
Daniel Kiss
9e9fa00dcb
[Arm][AArch64][Clang] Respect function's branch protection attributes. (#101978)
Default attributes assigned to all functions according to the command
line parameters. Some functions might have their own attributes and we
need to set or remove attributes accordingly.
Tests are updated to test this scenarios too.
2024-08-09 17:51:38 +02:00
Will Dietz
7a98071da2
[mlir] Verifier: steal bit to track seen instead of set. (#102626)
Tracking a set containing every block and operation visited can become
very expensive and is unnecessary.

Co-authored-by: Will Dietz <w@wdtz.org>
2024-08-09 10:50:25 -05:00
Yupei Liu
52126dc72c
[Clang] Fix Handling of Init Capture with Parameter Packs in LambdaScopeForCallOperatorInstantiationRAII (#100766)
This PR addresses issues related to the handling of `init capture` with
parameter packs in Clang's
`LambdaScopeForCallOperatorInstantiationRAII`.

Previously, `addInstantiatedCapturesToScope` would add `init capture`
containing packs to the scope using the type of the `init capture` to
determine the expanded pack size. However, this approach resulted in a
pack size of 0 because `getType()->containsUnexpandedParameterPack()`
returns `false`. After extensive testing, it appears that the correct
pack size can only be inferred from `getInit`.

But `getInit` may reference parameters and `init capture` from an outer
lambda, as shown in the following example:

```cpp
auto L = [](auto... z) {
    return [... w = z](auto... y) {
        // ...
    };
};
```

To address this, `addInstantiatedCapturesToScope` in
`LambdaScopeForCallOperatorInstantiationRAII` should be called last.
Additionally, `addInstantiatedCapturesToScope` has been modified to only
add `init capture` to the scope. The previous implementation incorrectly
called `MakeInstantiatedLocalArgPack` for other non-init captures
containing packs, resulting in a pack size of 0.

### Impact

This patch affects scenarios where
`LambdaScopeForCallOperatorInstantiationRAII` is passed with
`ShouldAddDeclsFromParentScope = false`, preventing the correct addition
of the current lambda's `init capture` to the scope. There are two main
scenarios for `ShouldAddDeclsFromParentScope = false`:

1. **Constraints**: Sometimes constraints are instantiated in place
rather than delayed. In this case,
`LambdaScopeForCallOperatorInstantiationRAII` does not need to add `init
capture` to the scope.
2. **`noexcept` Expressions**: The expressions inside `noexcept` have
already been transformed, and the packs referenced within have been
expanded. Only `RebuildLambdaInfo` needs to add the expanded captures to
the scope, without requiring `addInstantiatedCapturesToScope` from
`LambdaScopeForCallOperatorInstantiationRAII`.

### Considerations

An alternative approach could involve adding a data structure within the
lambda to record the expanded size of the `init capture` pack. However,
this would increase the lambda's size and require extensive
modifications.

This PR is a prerequisite for implmenting
https://github.com/llvm/llvm-project/issues/61426
2024-08-09 23:13:11 +08:00
Simon Pilgrim
669d8448a3 [X86] Convert truncsat clamping patterns to use SDPatternMatch. NFC.
Inspired by #99418 (which hopefully we can replace this code with at some point)
2024-08-09 16:11:36 +01:00
Nico Weber
f4d5b14dcc [gn] Give two scripts argparse.RawDescriptionHelpFormatter
Without this, the doc string is put in a single line. These
scripts have multi-line docstrings, so this makes their --help
output look much nicer.

Otherwise, no behavior change.
2024-08-09 11:10:12 -04:00
Haojian Wu
5c0eb1a6e4 [bazel] Add missing dep for the SPIRVToLLVM target 2024-08-09 16:52:09 +02:00
Joel E. Denny
3c639b83a6
[Clang] Simplify specifying passes via -Xoffload-linker (#102483)
Make it possible to do things like the following, regardless of whether
the offload target is nvptx or amdgpu:

```
$ clang -O1 -g -fopenmp --offload-arch=native test.c                       \
    -Xoffload-linker -mllvm=-pass-remarks=inline                           \
    -Xoffload-linker -mllvm=-force-remove-attribute=g.internalized:noinline\
    -Xoffload-linker --lto-newpm-passes='forceattrs,default<O1>'           \
    -Xoffload-linker --lto-debug-pass-manager                              \
    -foffload-lto
```

To accomplish that:

- In clang-linker-wrapper, do not forward options via `-Wl` if they
might have literal commas. Use `-Xlinker` instead.
- In clang-nvlink-wrapper, accept `--lto-debug-pass-manager` and
`--lto-newpm-passes`.
- In clang-nvlink-wrapper, drop `-passes` because it's inconsistent with
the interface of `lld`, which is used instead of clang-nvlink-wrapper
when the target is amdgpu. Without this patch, `-passes` is passed to
`nvlink`, producing an error anyway.

---------

Co-authored-by: Joseph Huber <huberjn@outlook.com>
2024-08-09 10:41:42 -04:00
Haojian Wu
3bd63d4aa7 [bazel] Port for d45de8003a269066c9a9af871119a7c36eeb5aa3 2024-08-09 16:40:35 +02:00
Manish Kausik H
259742a885
[SelectionDAG] Use unaligned store/load to move AVX registers onto stack for insertelement (#82130)
Prior to this patch, SelectionDAG generated aligned move onto stacks for
AVX registers when the function was marked as a no-realign-stack
function. This lead to misalignment between the stack and the
instruction generated. This patch fixes the issue. There was a similar
issue reported for `extractelement` which was fixed in
a6614ec5b7c1dbfc4b847884c5de780cf75e8e9c

Co-authored-by: Manish Kausik H <hmamishkausik@gmail.com>
2024-08-09 15:39:54 +01:00
Shilei Tian
ee8100ba02
[Clang][OMPX] Add the code generation for multi-dim num_teams (#101407)
This patch adds the code generation support for multi-dim `num_teams`
clause when it is used with `target teams ompx_bare` construct.
2024-08-09 10:33:41 -04:00
David Green
dad1cb9cf9 [ARM] Regenerate big-endian-vmov.ll. NFC 2024-08-09 15:24:54 +01:00
Ivan Kosarev
335bc3c0b2
[AMDGPU][AsmParser][NFCI] All NamedIntOperands to be of the i32 type. (#102616)
There's no need for them to have different types.

Part of <https://github.com/llvm/llvm-project/issues/62629>.
2024-08-09 15:20:48 +01:00
Job Henandez Lara
ff1cc5b97c
[libc][math][c23] Add totalorderl function. (#102564) 2024-08-09 10:18:00 -04:00
Angel Zhang
93fc4590d9
[mlir][spirv] Support memref in convert-to-spirv pass (#102534)
This PR adds conversion patterns for MemRef to the `convert-to-spirv`
pass, introduced in #95942. Conversions from MemRef memory space to
SPIR-V storage class were also included, and would run before the final
dialect conversion phase.

**Future Plans**
- Add tests for ops other than `memref.load` and `memref.store`

---------

Co-authored-by: Jakub Kuderski <kubakuderski@gmail.com>
2024-08-09 10:14:37 -04:00
Victor Perez
d45de8003a
[MLIR][GPU-LLVM] Convert gpu.func to llvm.func (#101664)
Add support in `-convert-gpu-to-llvm-spv` to convert `gpu.func` to
`llvm.func` operations.

- `spir_kernel`/`spir_func` calling conventions used for
kernels/functions.
- `workgroup` attributions encoded as additional `llvm.ptr<3>`
arguments.
- No attribute used to annotate kernels
- `reqd_work_group_size` attribute using to encode
`gpu.known_block_size`.
- `llvm.mlir.workgroup_attrib_size` used to encode workgroup attribution
sizes. This will be attached to the pointer argument workgroup
attributions lower to.

**Note**: A notable missing feature that will be addressed in a
follow-up PR is a `-use-bare-ptr-memref-call-conv` option to replace
MemRef arguments with bare pointers to the MemRef element types instead
of the current MemRef descriptor approach.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-08-09 16:09:11 +02:00
Ian Anderson
4c5ef66900
Fix a unit test input file (#102567)
I forgot to update the version info in the SDKSettings file when I
updated it to the real version relevant to the test.
2024-08-09 07:06:11 -07:00
Jacek Caban
1d77dd50f1
[llvm-readobj][COFF] Dump hybrid objects for ARM64X files. (#102245) 2024-08-09 15:55:28 +02:00
Matt Arsenault
cf54cae26b
AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (#102614)
This allows moving some tests relying on -stop-after=amdgpu-isel
to move to checking -stop-after=finalize-isel instead, which
will more reliably pass the verifier.
2024-08-09 17:52:41 +04:00
Nikita Popov
5bc1f9e5b0 [MemoryBuiltins] Simplify getCalledFunction() helper (NFC)
If nobuiltin is set, directly return nullptr instead of using a
separate out parameter and having all callers check this.
2024-08-09 15:46:31 +02:00
David Green
0b745a1084
[AArch64] Add invalid 1 x vscale costs for reductions and reduction-operations. (#102105)
The code-generator is currently not able to handle scalable vectors of
<vscale x 1 x eltty>. The usual "fix" for this until it is supported is
to mark the costs of loads/stores with an invalid cost, preventing the
vectorizer from vectorizing at those factors. But on rare occasions
loops do not contain load/stores, only reductions.

So whilst this is still unsupported return an invalid cost to avoid
selecting vscale x 1 VFs. The cost of a reduction is not currently used
by the vectorizer so this adds the cost to the add/mul/and/or/xor or
min/max that should feed the reduction. It includes reduction costs
too, for completeness. This change will be removed when code-generation
for these types is sufficiently reliable.

Fixes #99760
2024-08-09 14:25:07 +01:00
Nikita Popov
195362929c [MemoryBuiltins] Handle allocator attributes on call-site
We should handle allocator attributes not only on function
declarations, but also on the call-site. That way we can e.g.
also optimize cases where the allocator function is a virtual
function call.

This was already supported in some of the MemoryBuiltins helpers,
but not all of them. This adds support for allocsize, alloc-family
and allockind("free").
2024-08-09 15:22:54 +02:00
Ramkumar Ramachandra
fff78a51ee
LSV/test/AArch64: add missing lit.local.cfg; fix build (#102607)
Follow up on 199d6f2 (LSV: document hang reported in #37865) to fix the
build when omitting the AArch64 target. Add the missing lit.local.cfg.
2024-08-09 14:17:13 +01:00
Nikita Popov
a15de17772 Revert "Enable logf128 constant folding for hosts with 128bit floats (#96287)"
This reverts commit ccb2b011e577e861254f61df9c59494e9e122b38.

Causes buildbot failures, e.g. on ppc64le builders.
2024-08-09 15:12:11 +02:00
Anton Sidorenko
02645d66f9
[RISCV] Add Syntacore SCR5 RV32/64 processors definition (#102285)
Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core.
Overview: https://syntacore.com/products/scr5

Scheduling model will be added in a subsequent PR.

Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
2024-08-09 16:02:27 +03:00
Nikita Popov
0795ab4eba [InstCombine] Remove unnecessary RUN line from test (NFC)
As all the necessary information is encoded using attributes
nowadays, this test doesn't actually depend on the triple
anymore.
2024-08-09 14:57:35 +02:00