558235 Commits

Author SHA1 Message Date
Dan Liew
3ebed51e99
[Clang][LLDB] Refactor trap reason demangling out of LLDB and into Clang (#165996)
This patch refactors the trap reason demangling logic in
`lldb_private::VerboseTrapFrameRecognizer::RecognizeFrame` into a new
public function `clang::CodeGen::DemangleTrapReasonInDebugInfo`.

There are two reasons for doing this:

1. In a future patch the logic for demangling needs to be used somewhere
else in LLDB and thus the logic needs refactoring to avoid duplicating
code.
2. The logic for demangling shouldn't really be in LLDB anyway because
it's a Clang implementation detail and thus the logic really belongs
inside Clang, not LLDB.

Unit tests have been added for the new function that demonstrate how to
use the new API.

The function names recognized by VerboseTrapFrameRecognizer are
identical to before. However, this patch isn't NFC because:

* The `lldbTarget` library now links against `clangCodeGen` which it
didn't previously.
* The LLDB logging output is a little different now. The previous code
tried to log failures for an invalid regex pattern and for the
`Regex::match` API not returning the correct number of matches. These
failure conditions are unreachable via unit testing so they have been
made assertions failures inside the `DemangleTrapReasonInDebugInfo`
implementation instead of trying to log them in LLDB.

rdar://163230807
2025-11-04 16:25:33 -08:00
Jin Huang
fa5cd27ef0
[profcheck] Add unknown branch weights to expand LL/SR loop. (#166273)
As a follow-up to PR#165841, this change addresses `prof_md` metadata
loss in AtomicExpandPass when lowering `atomicrmw xchg` to a
Load-Linked/Store-Exclusive (LL/SC) loop.

This path is distinct from the LSE path addressed previously:

PR #165841 (and its tests) used `-mtriple=aarch64-linux-gnu`, which
targets a modern **ARMv8.1+** architecture. This architecture supports
**Large System Extensions (LSE)**, allowing `atomicrmw` to be lowered
directly to a more efficient hardware instruction.

This PR (and its tests) uses `-mtriple=aarch64--` or
`-mtriple=armv8-linux-gnueabihf`. This indicates an `ARMv8.0 or lower
architecture that does not support LSE`. On these targets, the pass must
fall back to synthesizing a manual LL/SC loop using the `ldaxr/stxr`
instruction pair.

Similar to previous issue, the new conditional branch was failin to
inherit the `prof_md` metadata. Theis PR correctly fix the branch
weights to the newly created branch within the LL/SC loop, ensuring
profile information is preserved.

Co-authored-by: Jin Huang <jingold@google.com>
2025-11-04 16:23:34 -08:00
Min-Yih Hsu
6d4e75cc93
[MISched][NFC] Rename isUnbufferedGroup to isReservedGroup (#166439)
In both ScheduleDAGInstrs and MachineScheduler, we call `BufferSize = 0`
as _reserved_ and `BufferSize = 1` as _unbuffered_. This convention is
stem from the fact that we set `SUnit::hasReservedResource` to true when
any of the SUnit's consumed resources has BufferSize equal to zero; set
`SUnit::isUnbuffered` to true when any of its consumed resources has
BufferSize equal to one.

However, `SchedBoundary::isUnbufferedGroup` doesn't really follow this
convention: it returns true when the resource in question is a
`ProcResGroup` and its BufferSize equals to **zero** rather than one.
This could be really confusing for the reader. This patch renames this
function to `isReservedGroup` in aligned with the convention mentioned
above.

NFC.
2025-11-04 16:21:37 -08:00
Marcell Leleszi
d8e56988f8
[libc] Add printf error handling (with fixes) (#166382)
https://github.com/llvm/llvm-project/issues/159474

Resubmitting https://github.com/llvm/llvm-project/pull/162876 with fixes
as it broke some buildbots:
 - Fix comparisons of integer expressions of different signedness
- Not check for specific errnos in tests, as they might not be available
on all platforms
2025-11-04 16:20:51 -08:00
Wenju He
8648beff75
[NFC][libclc] Rename clc_cbrt.inc to clc_cbrt.h (#166330)
__clc_cbrt functions are declared in clc_cbrt.inc. Rename to .h for
consistency with other headers.
2025-11-05 08:20:29 +08:00
Shubh Pachchigar
0fd029858a
[libc] Add chown and getgid implementations (#166434)
Implements chown and getgid per the POSIX specification and adds
corresponding unit tests. getgid is added as it is required by the chown
unit tests. This PR will address #165785

Co-authored-by: shubh@DOE <shubhp@mbm3a24.local>
2025-11-04 16:18:53 -08:00
Matt Arsenault
2b4ac66297
AMDGPU: Cleanup and modernize limit-coalesce.mir test (#166465) 2025-11-04 23:57:39 +00:00
Paul Kirth
dc3b5141cd
[llvm][mustache] Optimize accessor splitting with a single pass (#159198)
The splitMustacheString function previously used a loop of
StringRef::split and StringRef::trim. This was inefficient as
it scanned each segment of the accessor string multiple times.

This change introduces a custom splitAndTrim function that
performs both operations in a single pass over the string,
reducing redundant work and improving performance, most notably
in the number of CPU cycles executed.

| Metric | Baseline | Optimized | Change |
| --- | --- | --- | --- |
| Time (ms) | 35\.57 | 35\.36 | \-0.59% |
| Cycles | 34\.91M | 34\.26M | \-1.86% |
| Instructions | 85\.54M | 85\.24M | \-0.35% |
| Branch Misses | 111\.9K | 112\.2K | \+0.27% |
| Cache Misses | 242\.1K | 239\.9K | \-0.91% |
2025-11-04 23:56:00 +00:00
A. Jiang
4cdeb7d292
[libc++] Remove guards for builtins for reference binding traits (#166288)
We're only supporting Clang 20+ and Apple Clang 17 now, where these
builtins are universally implemented.
2025-11-05 07:24:59 +08:00
yonghong-song
ac5b615197
[BPF] Remove dead code related to __bpf_trap global var (#166440)
In [1], the symbol __bpf_trap (macro BPF_TRAP) is removed if it is not
used in the code. In the discussion in [1], it is found that the branch
"if (Op.isSymbol())" is actually always false. Remove it to avoid
confusion.

  [1] https://github.com/llvm/llvm-project/pull/166003
2025-11-04 15:15:33 -08:00
Andrew Haberlandt
a51d219ee7
[sanitizer_common] Add arm64e module type (#166018)
This will fix some symbolication failures on arm64e machines when the
symbolicator passes the (wrong) architecture string to atos.
2025-11-04 14:32:06 -08:00
Nikolas Klauser
d4222bf9e2
[libc++] Use saturation builtins directly for {add,sub}_sat (#165228)
This doesn't improve performance (except with optimizations disabled),
since the compiler is able to fold our current implementation. However,
it does significantly reduce the amount of code the compiler has to sift
through, reducing compile times a bit.
2025-11-04 23:29:13 +01:00
Min-Yih Hsu
c93df83b04
[opt-viewer] Account for optimization records YAML files generated by LTO (#135059)
The optimization records YAML files generated by Clang's LTO pipeline
are named "\*.opt.ld.yaml" rather than "\*.opt.yaml". This patch adds
that pattern into the search list of `find_opt_files` as well.
2025-11-04 22:03:45 +00:00
David Green
cf73a0b102
[AArch64] Copy implicit def operands when creating LDP. (#164253)
Otherwise we might end up with undefined register uses. Copying implicit
uses can cause problems where a register is both defined and used in the
same LDP, so I have not tried to add them here.

Fixes #164230
2025-11-04 21:55:57 +00:00
Han-Chung Wang
b21949eb34
Revert "[mlir][memref]: Collapse strided unit dim even if strides are dynamic" (#166448)
Reverts llvm/llvm-project#157330

The original revision introduces a bug in `isGuaranteedCollapsible`. The
`memref<3x3x1x96xf32, strided<[288, 96, 96, 1], offset: 864>>` is no
longer collapsable with the change. The revision reverts the change to
bring back correct behavior. `stride` should be computed as `96` like
the old behavior in the failed iteration.


92a1eb3712/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp (L2597-L2605)
2025-11-04 21:49:46 +00:00
Alireza Torabian
025e431e74
[LoopFusion] Forget loop and block dispositions after latch merge (#166233)
Merging the latches of loops may affect the dispositions, so they should
be forgotten after the merge. This patch fixed the crash in loop fusion
[#164082](https://github.com/llvm/llvm-project/issues/164082).
2025-11-04 16:48:39 -05:00
Saleem Abdulrasool
8cd22447af
AArch64: correct preserve_most and preserve_all on Windows (#166436)
This fixes register information handling for the `preserve_most` and
`preserve_all` calling conventions on Windows ARM64.

The root issue was cascading `if` statements whose behavior depended on
their order. This patch makes the minimal, tactical change needed for
Swift’s two calling conventions, unblocking current work. A broader
refactor to remove the ordering dependency is still desired and will
follow in a subsequent PR.
2025-11-04 21:40:42 +00:00
Syadus Sefat
ce091da5df
[AMDGPU] Mark WMMA machine instructions as convergent (#165602)
The WMMA MI(s) are missing the isConvergent flag. This causes incorrect
behavior in passes like machine-sink, where WMMA instructions get sunk
into divergent branches.

This patch fixes the issue by setting the isConvergent flag to 1 in the
VOP3PInstructions.td file.
2025-11-04 15:37:27 -06:00
Paul Kirth
1c85981e37
[llvm][mustache] Avoid redundant saves in accessor splitting (#159197)
The splitMustacheString function was saving StringRefs that
were already backed by an arena-allocated string. This was
unnecessary work. This change removes the redundant
Ctx.Saver.save() call.

This optimization provides a small but measurable performance
improvement on top of the single-pass tokenizer, most notably
reducing branch misses.

  Metric         | Baseline | Optimized | Change
  -------------- | -------- | --------- | -------
  Time (ms)      | 35.77    | 35.57     | -0.56%
  Cycles         | 35.16M   | 34.91M    | -0.71%
  Instructions   | 85.77M   | 85.54M    | -0.27%
  Branch Misses  | 113.9K   | 111.9K    | -1.76%
  Cache Misses   | 237.7K   | 242.1K    | +1.85%
2025-11-04 13:21:04 -08:00
Kaitlin Peng
6e2dcdb17c
Fix implicit truncation of select non-bool vector conditions (#166279)
Fixes #164018. 

The problem is that we're unable to do an implicit conversion sequence
on a template deduced argument, so the current vector templates can't
reconcile `vector<int, 4>` with `vector<bool, Sz>`. This PR separates
the vector templates into size-specific ones, getting rid of the `Sz`
deduction and allowing for the implicit conversion to be done.
2025-11-04 13:20:46 -08:00
Charitha Saumya
9703bda95b
[mlir][xegpu] Add OptimizeBlockLoads pass. (#165483)
This pass rewrites certain xegpu `CreateNd` and `LoadNd` operations that
feeds into `vector.transpose` to more optimal form to improve
performance. Specifically, low precision (bitwidth < 32) `LoadNd` ops
that feeds into transpose ops are rewritten to i32 loads with a valid
transpose layout such that later passes can use the load with transpose
HW feature to accelerate such load ops.

**Update:**
Pass is renamed to `OptimizeBlockLoads ` because later we plan to add
the array length optimization into this pass as well. This will break
down a larger load (like `32x32xf16`) into more DPAS-favorable array
length loads (`32x16xf16` with array length = 2). Both these
optmizations require rewriting `CreateNd` and `LoadNd` and it makes
sense to have a common pass for both.
2025-11-04 13:15:32 -08:00
Adrian Prantl
2141edf506 [lldb] Skip tests on older versions of clang 2025-11-04 12:53:23 -08:00
Nick Sarnie
4f428d30e4
[clang][lit] Add SPIR-V to some OpenMP offload tests (#165775)
Just to get a little more test coverage.

Signed-off-by: Nick Sarnie <nick.sarnie@intel.com>
2025-11-04 20:34:42 +00:00
Amr Hesham
240fe7e844
[CIR][NFC] EHScope & Cleanups Iterators and operators overloading (#165317)
Upstream EHScope & Cleanup iterators, helpers and operator overloading
as a prerequisite for #165158

Issue https://github.com/llvm/llvm-project/issues/154992
2025-11-04 21:21:56 +01:00
Hans Wennborg
6f91f588d9
build_llvm_release.bat: Put the 32-bit sanitizers back (#166437)
Follow-up to bcb3d2f5122276ed9969fe2b2ef4428652800377.

Even though 32-bit win/asan is not well supported, we shouldn't drop it
without some discussion at least. Also, we probably shouldn't drop the
other sanitizers that are gated by COMPILER_RT_BUILD_SANITIZERS.

The tests no longer pass after switching to the runtimes build however
(I believe that build mode runs more of the tests?), so disable them.
2025-11-04 21:19:32 +01:00
Tuomas Kärnä
718818a5cb
[MLIR][Linalg][Transform] Expose more args in VectorizeChildren[...] op's Python bindings (#166134)
Expose missing boolean arguments in
`VectorizeChildrenAndApplyPatternsOp` Python bindings.
2025-11-04 20:08:42 +00:00
Kai Nacke
2a65fab965
[z/OS] Improve compiler options on z/OS (#166415)
`_XPLATFORM_SOURCE` needs to be defined to improve source code
compatibility (e.g. for `O_CLOEXEC`). The define `_UNIX03_THREADS` can
be removed, because it is automatically set by `_XOPEN_SOURCE=600`.

See the documentation of feature test macros:
https://www.ibm.com/docs/en/zos/3.1.0?topic=files-feature-test-macros

Tested on z/OS 3.1 with the Open XL C/C++ 2.2 compiler.
2025-11-04 15:07:20 -05:00
choikwa
8f683c3e4b
[AMDGPU] NFC, delete promote-alloca testcase (#166297)
previous merge did not delete.
2025-11-04 14:34:54 -05:00
Baranov Victor
a99e13271e
[Docs][clang-tools-extra] Convert maintainers list to .rst format (#165171)
[Clang maintainers
list](https://github.com/llvm/llvm-project/blob/main/clang/Maintainers.rst)
is already in `.rst` format, which gives nice visuals.
I think we should convert clang-tools-extra maintainers too to `.rst`.
2025-11-04 22:32:43 +03:00
yonghong-song
7272a6c888
[BPF] Avoid relocation for jumptable entries (#166301)
Currently, the jump table entry contains labels only. For example, the
following is one example:

  BPF.JT.0.0:
        .quad   LBB0_1
        .quad   LBB0_2
        .size   BPF.JT.0.0, 16

Since the jump table entry contains a label, the relocation is necessary
so linker can resolve the label value. The relocation looks like below:

  Relocation section '.rel.jumptables' at offset 0x160 contains 2 entries:
      Offset             Info             Type               Symbol's Value  Symbol's Name
  0000000000000000  0000000200000002 R_BPF_64_ABS64         0000000000000000 .text
  0000000000000008  0000000200000002 R_BPF_64_ABS64         0000000000000000 .text

You can see that the symbol value is 0 which makes .rel.jumptables not
very useful.

Instead of having the label itself in the jump table entry, use the
difference of label and the section begin symbol. This can avoid the
relocation and the eventual jumptable entries in object file remains the
same as before.

  Hex dump of section '.jumptables':
  0x00000000 68000000 00000000 78000000 00000000 h.......x.......
2025-11-04 11:32:12 -08:00
Aiden Grossman
e03fac127c
[X86][NewPM] Port X86PartialReduction to NewPM
There are no tests that specifically stop/start at
x86-partial-reduction, so no test cases have been updated for this
patch.

Reviewers: phoebewang, paperchalice, RKSimon, arsenm

Reviewed By: arsenm, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/166048
2025-11-04 11:28:27 -08:00
Aiden Grossman
4776451693
[X86][NewPM] Port lower-amx-intrinsics to NewPM
Reviewers: paperchalice, phoebewang, arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/165113
2025-11-04 11:27:38 -08:00
Ross Burton
0ae0ac0f00
[cmake] Pass PYTHON_EXECUTABLE to native builds (#163574)
Ensure that the nested native build uses the same python interpreter as
the main build, in case the python that CMake detects first is not the
python that the user has specified explicitly.

For example, if the person building LLVM wants to use a different python
interpreter to build (eg, testing the build with `python3.14` when
`python3` is a link to `python3.8`, or the default python doesn't have
development headers available) then they could add
`-DPYTHON_EXECUTABLE=python3.14` when invoking CMake. This should be
forwarded to the native CMake build to ensure that the same python is
used.

Original fix by Anuj Mittal <anuj.mittal@intel.com>.
2025-11-04 11:26:02 -08:00
nerix
5be12e1c95
[LLDB] Run API tests with PDB too (#149305)
From
https://github.com/llvm/llvm-project/pull/148554#issuecomment-3083261858
- this adds an option for API tests to be run with the both PDB readers
on Windows. As there are a lot of failures with PDB, this is an opt-in
per test.

To get PDB, `-g -gcodeview` has to be used on Clang. `-gcodeview` alone
isn't enough, because it won't cause clang to pass `-debug` to the
linker.

#149498 tracks the (currently) failing tests.
2025-11-04 20:23:33 +01:00
Matt Arsenault
e5f191e171 DeclareRuntimeLibcalls: Add registered target checks to test run lines 2025-11-04 11:23:02 -08:00
Robert Imschweiler
dc94f2cbad
[Offload] Add device UID (#164391)
Introduced in OpenMP 6.0, the device UID shall be a unique identifier of
a device on a given system. (Not necessarily a UUID.) Since it is not
guaranteed that the (U)UIDs defined by the device vendor libraries, such
as HSA, do not overlap with those of other vendors, the device UIDs in
offload are always combined with the offload plugin name. In case the
vendor library does not specify any device UID for a given device, we
fall back to the offload-internal device ID.
The device UID can be retrieved using the `llvm-offload-device-info`
tool.
2025-11-04 20:15:47 +01:00
Matt Arsenault
92a1eb3712 AArch64: Regenerate cost model tests
Broken by 831e79adff4506a0b22a770dcaa46bf5a37257cb, though
presubmit was somehow green.
2025-11-04 11:08:47 -08:00
yasmincs
fe5c3cbbd0
Added Conditions of SM90 and ISA7.8 for Using cvt.ftz.f32.bf16 Instruction (#165774)
Updated the conditions for generating the cvt.ftz.f32.bf16 instruction
to include sm90 and isa7.8, so that ftz is only generated when it is
supported.

---------

Co-authored-by: Justin Fargnoli <jfargnoli@nvidia.com>
2025-11-04 14:02:49 -05:00
Grigory Pastukhov
7398591148
[CodeGen] Add skipFunction() check to MachineFunctionSplitter (#166260)
MachineFunctionSplitter was missing a skipFunction() check, causing it
to incorrectly split functions that should be skipped (e.g., functions
with optnone attribute).

This patch adds an early skipFunction() check in runOnMachineFunction()
to ensure these functions are never split, regardless of profile data
availability or other splitting conditions.
2025-11-04 11:01:50 -08:00
Mircea Trofin
2bc22ea02e
[NFC][SLU] Update SimpleLoopUnswitch/guards.ll (#166285)
When running UTC on SLU/guards.ll (without LLVM changes), there are a number of changes in the UTC-generated checks. Submitting those first to simplify the diff of PR #164271, as most of the changes in the latter were actually these.
2025-11-04 11:00:35 -08:00
Sam Clegg
e29ee27061
[lld][WebAssembly] Allow --no-stack-first in addition to --stack-first (#166384)
This paves the way to make `--stack-first` the default.

See: #151015
2025-11-04 18:40:46 +00:00
Florian Hahn
290ff955f0
[VPlan] Verify incoming values of VPIRPhi matches before checking (NFC)
Update the verifier to first check if the number of incoming values
matches the number of predecessors, before using
incoming_values_and_blocks. We unfortunately need also check here, as
this may be called before verifyPhiRecipes runs.

Also update the verifier unit tests, to actually fail for the expected
recipes.
2025-11-04 18:34:14 +00:00
Sp00ph
2e8543c735
[X86] Improve variable 8-bit shifts on AVX512BW (#164136)
Previously, `clang -march=znver5 -O3` would emit the following for
`shl`, `lshr` and `ashr <64 x i8>`:
```asm
.LCPI0_2:
	.byte	8
	.byte	4
	.byte	2
	.byte	1
	.byte	0
	.byte	0
	.byte	0
	.byte	0
.LCPI0_3:
	.byte	32
	.byte	16
	.byte	8
	.byte	4
	.byte	2
	.byte	1
	.byte	0
	.byte	0
shl:
	vpsllw	zmm1, zmm1, 5
	vpmovb2m	k1, zmm1
	vpaddb	zmm1, zmm1, zmm1
	vgf2p8affineqb	zmm0 {k1}, zmm0, qword ptr [rip + .LCPI0_2]{1to8}, 0
	vpmovb2m	k1, zmm1
	vpaddb	zmm1, zmm1, zmm1
	vgf2p8affineqb	zmm0 {k1}, zmm0, qword ptr [rip + .LCPI0_3]{1to8}, 0
	vpmovb2m	k1, zmm1
	vpaddb	zmm0 {k1}, zmm0, zmm0
	ret

.LCPI1_3:
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	128
	.byte	64
	.byte	32
	.byte	16
.LCPI1_4:
	.byte	0
	.byte	0
	.byte	128
	.byte	64
	.byte	32
	.byte	16
	.byte	8
	.byte	4
.LCPI1_5:
	.byte	0
	.byte	128
	.byte	64
	.byte	32
	.byte	16
	.byte	8
	.byte	4
	.byte	2
lshr:
	vpsllw	zmm1, zmm1, 5
	vpmovb2m	k1, zmm1
	vpaddb	zmm1, zmm1, zmm1
	vgf2p8affineqb	zmm0 {k1}, zmm0, qword ptr [rip + .LCPI1_3]{1to8}, 0
	vpmovb2m	k1, zmm1
	vpaddb	zmm1, zmm1, zmm1
	vgf2p8affineqb	zmm0 {k1}, zmm0, qword ptr [rip + .LCPI1_4]{1to8}, 0
	vpmovb2m	k1, zmm1
	vgf2p8affineqb	zmm0 {k1}, zmm0, qword ptr [rip + .LCPI1_5]{1to8}, 0
	ret

ashr:
	vpsllw	zmm1, zmm1, 5
	vpunpckhbw	zmm2, zmm0, zmm0
	vpunpckhbw	zmm4, zmm1, zmm1
	vpsraw	zmm3, zmm2, 4
	vpunpcklbw	zmm0, zmm0, zmm0
	vpmovb2m	k1, zmm4
	vpaddw	zmm4, zmm4, zmm4
	vpunpcklbw	zmm1, zmm1, zmm1
	vmovdqu8	zmm2 {k1}, zmm3
	vpmovb2m	k1, zmm4
	vpsraw	zmm3, zmm2, 2
	vpaddw	zmm4, zmm4, zmm4
	vmovdqu8	zmm2 {k1}, zmm3
	vpsraw	zmm3, zmm2, 1
	vpmovb2m	k1, zmm4
	vmovdqu8	zmm2 {k1}, zmm3
	vpmovb2m	k1, zmm1
	vpsraw	zmm3, zmm0, 4
	vpaddw	zmm1, zmm1, zmm1
	vpsrlw	zmm2, zmm2, 8
	vmovdqu8	zmm0 {k1}, zmm3
	vpmovb2m	k1, zmm1
	vpsraw	zmm3, zmm0, 2
	vpaddw	zmm1, zmm1, zmm1
	vmovdqu8	zmm0 {k1}, zmm3
	vpsraw	zmm3, zmm0, 1
	vpmovb2m	k1, zmm1
	vmovdqu8	zmm0 {k1}, zmm3
	vpsrlw	zmm0, zmm0, 8
	vpackuswb	zmm0, zmm0, zmm2
	ret
```

With this commit, the generated assembly becomes this:

```asm
.LCPI0_2:
	.byte	0
	.byte	255
	.byte	0
	.byte	255
.LCPI0_3:
	.byte	255
	.byte	0
	.byte	255
	.byte	0
shl:
	vpsrlw	zmm2, zmm1, 8
	vpandd	zmm3, zmm0, dword ptr [rip + .LCPI0_2]{1to16}
	vpandd	zmm1, zmm1, dword ptr [rip + .LCPI0_3]{1to16}
	movabs	rax, -6148914691236517206
	kmovq	k1, rax
	vpsllvw	zmm2, zmm3, zmm2
	vpsllvw	zmm0, zmm0, zmm1
	vmovdqu8	zmm0 {k1}, zmm2
	ret

.LCPI1_0:
	.byte	255
	.byte	0
lshr:
	vpbroadcastw	zmm2, word ptr [rip + .LCPI1_0]
	movabs	rax, -6148914691236517206
	kmovq	k1, rax
	vpandq	zmm3, zmm1, zmm2
	vpandq	zmm2, zmm0, zmm2
	vpsrlw	zmm1, zmm1, 8
	vpsrlvw	zmm2, zmm2, zmm3
	vpsrlvw	zmm0, zmm0, zmm1
	vmovdqu8	zmm2 {k1}, zmm0
	vmovdqa64	zmm0, zmm2
	ret

.LCPI2_1:
	.byte	255
	.byte	0
	.byte	255
	.byte	0
ashr:
	vpsrlw	zmm2, zmm1, 8
	vpandd	zmm1, zmm1, dword ptr [rip + .LCPI2_1]{1to16}
	movabs	rax, -6148914691236517206
	vpsravw	zmm2, zmm0, zmm2
	vpsllw	zmm0, zmm0, 8
	kmovq	k1, rax
	vpsraw	zmm0, zmm0, 8
	vpsravw	zmm0, zmm0, zmm1
	vmovdqu8	zmm0 {k1}, zmm2
	ret
```

While I don't have AVX512 hardware, llvm-mca suggests significant
speedups, and I've done some simple correctness tests on random inputs
using the Intel Software Development Emulator.
2025-11-04 18:32:55 +00:00
Matt Arsenault
831e79adff
DAG: Merge all sincos_stret emission code into legalizer (#166295)
This avoids AArch64 legality rules depending on libcall
availability.

ARM, AArch64, and X86 all had custom lowering of fsincos which
all were just to emit calls to sincos_stret / sincosf_stret. This
messes with the cost heuristics around legality, because really
it's an expand/libcall cost and not a favorable custom.

This is a bit ugly, because we're emitting code trying to match the
C ABI lowered IR type for the aggregate return type. This now also
gives an easy way to lift the unhandled x86_32 darwin case, since
ARM already handled the return as sret case.
2025-11-04 10:20:00 -08:00
Matt Arsenault
fe106b6e73
BasicTTI: Cleanup multiple result intrinsic handling (#165970)
Avoid weird lambda returning function pointer and sink the libcall
logic to where the operation is handled. This allows chaining the
libcall logic to try sincos_stret and fallback to sincos. The resulting
cost seems too low.
2025-11-04 10:19:32 -08:00
Amr Hesham
8ee1803538
[CIR] Upstream Builtin ExpOp (#166061)
Upstream the Builtin ExpOp
2025-11-04 18:12:41 +00:00
Matt Arsenault
fb21f16fe6
RuntimeLibcalls: Add stub API for getting function signatures (#166290)
Eventually this should be generated by tablegen for all functions.
For now add a manually implementation for sincos_stret, which I
have an immediate use for. This will allow pulling repeated code
across targets into shared call sequence code.

Also add sqrt just to make sure we can handle adding return attributes
on the declaration.
2025-11-04 10:06:29 -08:00
actink
6217f351bb
[NFC][AMDGPU] use DAG.UpdateNodeOperands update chain (#166396) 2025-11-04 10:03:02 -08:00
Craig Topper
8208591f27
[RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312)
This is consistent with some other nodes that require a constant.
Particularly intrinsics with ImmArg.
2025-11-04 09:56:59 -08:00
Simon Pilgrim
208b736015
[X86] select-copy.mir - regenerate test checks. NFC (#166405) 2025-11-04 17:55:06 +00:00