58 Commits

Author SHA1 Message Date
Sylvestre Ledru
395a369056 [Xtensa] Fix build after splitting SDNode::use_iterator
Same as: 145ddf7ede28d9131a65b7f86ad07736a824ee21
2024-12-19 19:52:53 +01:00
Andrei Safronov
c6967efe78
[Xtensa] Implement Code Density Option. (#119639)
The Code Density option adds 16-bit encoding for frequently used
instructions.
2024-12-18 15:37:08 +03:00
Andrei Safronov
be4a18387c
[Xtensa] Implement vararg support. (#117126) 2024-12-12 03:19:31 +03:00
Nikita Popov
4715dec8c0 [XTensa] Use getSignedConstant() for negative values 2024-11-25 14:43:11 +01:00
Matin Raayai
eec21ccee0
Fixed un-renamed CodeGenTargetMachineImpl Intheritances in Experimental Targets (#116290)
This PR fixes a set of build issues with experimental targets happened
in result of merging #111234 to master.
2024-11-14 16:29:06 -08:00
Matin Raayai
bb3f5e1fed
Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)
Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks
2024-11-14 13:30:05 -08:00
Fangrui Song
7111d031f1 [Xtensa] Fix Clang -Wundefined-bool-conversion after #113450 2024-11-10 09:54:22 -08:00
Andrei Safronov
3b1b1271fb
[Xtensa] Implement support for the BranchRelaxation. (#113450) 2024-11-08 01:50:42 +03:00
Sergei Barannikov
eeb987f6f3
[MC] Make generated MCInstPrinter::getMnemonic const (NFC) (#114682)
The value returned from the function depends only on the instruction opcode.

As a drive-by, change the type of the argument to const-reference.
2024-11-03 20:37:26 +03:00
Fangrui Song
facdae62b7 [MCInstPrinter] Make printRegName non-const
Similar to printInst. printRegName may change states (e.g. #113834).
2024-10-29 19:14:54 -07:00
Andrei Safronov
1e9a296557
[Xtensa] Implement branch analysis. (#110959) 2024-10-22 11:59:37 +03:00
Alex Rønne Petersen
ad4a582fd9
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.
2024-10-18 09:35:42 +04:00
Andrei Safronov
56736c7937
[Xtensa] Implement volatile load/store. (#110292)
Add a memory wait "MEMW" instruction before volatile load/store
operations, as implemented in GCC.
2024-10-03 08:35:27 +03:00
Andrei Safronov
dc2d0d5e1a
[Xtensa] Add basic support for inline asm constraints. (#108986) 2024-09-25 14:02:58 +03:00
Fangrui Song
e06f32114d [CSKY,M68k,Xtensa] Update function names after #108643 2024-09-18 10:48:45 -07:00
Andrei Safronov
0ba8b247dd
[Xtensa] Lowering FRAMEADDR/RETURNADDR operations. (#107363) 2024-09-13 21:33:54 +03:00
Piyou Chen
b01c006f73
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.

This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.
2024-08-27 10:08:43 +08:00
Andrei Safronov
ea625f48ab
[Xtensa] Implement sextload i8 (#106053) 2024-08-26 17:21:34 +02:00
Andrei Safronov
fab515ca7f
[Xtensa] Implement lowering Mul/Div/Shift operations. (#99981)
Implement lowering of the Mul/Div operations and also shift parts
operations. Implement lowering of the bit manipulations, like
ROT/SWAP/CTPOP/CTTZ/CTLZ.
2024-08-22 10:34:21 +02:00
Fangrui Song
8f14e39e59 [MC] Remove unnecessary isVerboseAsm from Target::AsmTargetStreamerCtorTy
The parameter is confusing as it duplicates MCStreamer::isVeboseAsm
(initialized from MCTargetOptions::AsmVerbose). After
233cca169237b91d16092c82bd55ee6a283afe98, no in-tree target uses the
parameter.
2024-07-21 10:19:17 -07:00
Matt Arsenault
0f0cfcff2c
CodeGen: Avoid some references to MachineFunction's getMMI (#99652)
MachineFunction's probably should not include a backreference to
the owning MachineModuleInfo. Most of these references were used
just to query the MCContext, which MachineFunction already directly
stores. Other contexts are using it to query the LLVMContext, which
can already be accessed through the IR function reference.
2024-07-19 22:09:05 +04:00
Sylvestre Ledru
64f67a4487 adjust the Xtensa backend after change f270a4dd6667759d7305797a077ae09648318ac7
Similar fix as in 3941f652317d95cac203e64791bfa730de7bbd1e
2024-07-17 13:48:12 +02:00
c8ef
3f222f3bc6
[NFC] Fix some typos (#98791) 2024-07-14 13:28:11 +02:00
Andrei Safronov
ce92b2f594
[Xtensa] Implement lowering SELECT_CC, SETCC. (#97017) 2024-07-11 09:46:24 +02:00
Fangrui Song
e25e8003ca MCExpr::evaluateAsRelocatable: replace the MCAsmLayout parameter with MCAssembler
Continue the MCAsmLayout removal work started by 67957a45ee1ec42ae1671cdbfa0d73127346cc95.
2024-07-01 16:23:43 -07:00
Fangrui Song
88c0a82588 [MC] Make MCAsmBackend::fixupNeedsRelaxation not pure virtual
This hook only needs to be implemented if mayNeedRelaxation may return
true.
2024-07-01 13:46:30 -07:00
Andrei Safronov
cc8fdd60c2
[Xtensa] Lower GlobalAddress/BlockAddress/JumpTable (#95256)
This patch implements lowering of the GlobalAddress, BlockAddress,
JumpTable and BR_JT. Also patch adds legal support of the BR_CC
operation for i32 type.
2024-06-25 12:21:33 +02:00
Andrei Safronov
52d87de7a4
[Xtensa] Fix register asm parsing. (#95551)
Fix passing temporary string object as argument to the StringRef
constructor in "parseRegister" function, because it causes errors in the
test "llvm/test/MC/Xtensa/Core/processor-control.s".
2024-06-17 13:26:20 +02:00
Fangrui Song
dd82fd4744 [Xtensa] Fix Clang warnings after #92960 2024-06-04 16:47:28 -07:00
Andrei Safronov
78f5d9cdba
[PATCH] [Xtensa] Implement FrameLowering methods and stack operation lowering. (#92960)
Implement emitPrologue/emitEpilogue methods, determine/spill/restore
callee saved registers functionality with test. Also implement lowering
of the DYNAMIC_STACKALLOC/STACKSAVE/STACKRESTORE stack operations with
tests.
2024-06-04 16:44:59 +02:00
paperchalice
7652a59407
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly
2024-06-04 08:10:58 +08:00
paperchalice
8917afaf0e
Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1

It still breaks EXPENSIVE_CHECKS build. Sorry.
2024-06-02 14:31:52 +08:00
paperchalice
d2cdc8ab45
[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.
2024-06-02 09:12:33 +08:00
Andrei Safronov
36209d366d
[Xtensa] Implement base CallConvention. (#83280)
Implement base Calling Convention functionality. 
Implement stack load/store register operations.
Implement call lowering.
2024-04-24 00:00:59 +02:00
Sergei Barannikov
5e5b656102
[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444) 2024-03-25 05:13:48 +03:00
Andrei Safronov
b5046a7fa9
[Xtensa] Initial codegen support from IR (#78548)
This PR provides implementation of the basic codegen infra such as
TargetFrameLowering, MCInstLower,
AsmPrinter, RegisterInfo, InstructionInfo, TargetLowering,
SelectionDAGISel.

Migrated from https://reviews.llvm.org/D145658
2024-02-12 17:41:59 +01:00
Kazu Hirata
395f9ce30e Use StringRef::{starts,ends}_with (NFC)
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
2023-12-16 10:14:44 -08:00
Kazu Hirata
4a0ccfa865 Use llvm::endianness::{big,little,native} (NFC)
Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces support::{big,little,native} with
llvm::endianness::{big,little,native}.
2023-10-12 21:21:45 -07:00
Arthur Eubanks
0a1aa6cda2
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.

This matches other nearby enums.

For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::
2023-09-14 14:10:14 -07:00
Sergei Barannikov
a479be0f39 [MC] Change tryParseRegister to return ParseStatus (NFC)
This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).
2023-09-06 10:28:12 +03:00
Fangrui Song
5be7f2a943 [MC,AArch64] Suppress local symbol to STT_SECTION conversion for GOT relocations
Assemblers change certain relocations referencing a local symbol to
reference the section symbol instead. This conversion is disabled for
many conditions (`shouldRelocateWithSymbol`), e.g. TLS symbol, for most
targets (including AArch32, x86, PowerPC, and RISC-V) GOT-generating
relocations.

However, AArch64 encodes the GOT-generating intent in MCValue::RefKind
instead of MCSymbolRef::Kind (see commit
0999cbd0b9ed8aa893cce10d681dec6d54b200ad (2014)), therefore not affected
by the code `case MCSymbolRefExpr::VK_GOT:`. As GNU ld and ld.lld
create GOT entries based on the symbol, ignoring addend, the two ldr
instructions will share the same GOT entry, which is not expected:
```
ldr     x1, [x1, :got_lo12:x]  // converted to .data+0
ldr     x1, [x1, :got_lo12:y]  // converted to .data+4

.data
// .globl x, y  would suppress STT_SECTION conversion
x:
.zero 4
y:
.long 42
```

This patch changes AArch64 to suppress local symbol to STT_SECTION
conversion for GOT relocations, matching most other targets. x and y
will use different GOT entries, which IMO is the most sensable behavior.

With this change, the ABI decision on https://github.com/ARM-software/abi-aa/issues/217
will only affect relocations explicitly referencing STT_SECTION symbols, e.g.
```
ldr     x1, [x1, :got_lo12:(.data+0)]
ldr     x1, [x1, :got_lo12:(.data+4)]
// I consider this unreasonable uses
```

IMO all reasonable use cases are unaffected.

Link: https://github.com/llvm/llvm-project/issues/63418
GNU assembler PR: https://sourceware.org/bugzilla/show_bug.cgi?id=30788

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D158577
2023-08-29 11:07:12 -07:00
Sergei Barannikov
0e79111e4d [AVR][BPF][Lanai][Xtensa] Replace OperandMatchResultTy with ParseStatus (NFC)
ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
  return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
  Error(L, "msg");
  return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D158275
2023-08-20 14:20:28 +03:00
Sergei Barannikov
fda24e86a5 [MC/AsmParser] Remove no-op overrides of parseDirective (NFC)
Remove overrides of parseDirective that unconditionally return NoMatch.
This is what the base implementation does.

This is a follow-up to D154101 based on post-commit review feedback.
2023-07-05 00:01:55 +03:00
Sergei Barannikov
af20c1c129 [MC] Add three-state parseDirective as a replacement for ParseDirective
Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third state: the
directive is not target specific. AsmParser::parseStatement detected
this case by using a fragile heuristic: if the target parser did not
consume any tokens, the directive is assumed to be not target-specific.

Some targets fail to follow the convention: they return success after
emitting an error or do not consume the entire line and return failure
on successful parsing. This was partially worked around by checking for
pending errors in parseStatement.

This patch tries to improve the situation by introducing parseDirective
method that returns ParseStatus -- three-state class. The new method
should eventually replace the old one returning bool.

ParseStatus is intentionally implicitly constructible from bool to allow
uses like `return Error(Loc, "message")`. It also has a potential to
replace OperandMatchResulTy as it is more convenient to use due to the
implicit construction from bool and more type safe.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D154101
2023-07-01 04:33:28 +03:00
Fangrui Song
0e9409d926 [Xtensa] Use parseOptionalToken. NFC 2023-06-15 11:51:52 -07:00
Fangrui Song
c6a69446e1 [M68k,MSP430,VE,Xtensa] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC 2023-06-06 21:02:52 -07:00
Fangrui Song
432caca39a Simplify with hasFeature. NFC 2023-02-17 18:22:24 -08:00
Archibald Elliott
62c7f035b4 [NFC][TargetParser] Remove llvm/ADT/Triple.h
I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.
2023-02-07 12:39:46 +00:00
Bjorn Pettersson
2dd221fe48 Remove no longer needed includes of LegacyPassManager.h
Most of the removed includes should probably have been removed already
when we removed TargetMachine::adjustPassManager.
2023-02-06 13:38:57 +01:00
Sergei Barannikov
6ae84d668f [MC] Use MCRegister instead of unsigned in MCInstPrinter (NFC)
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140654
2023-01-17 22:39:39 +03:00